Large inverse tunneling magnetoresistance in Co2_2Cr0.6_{0.6}Fe0.4_{0.4}Al/MgO/CoFe magnetic tunnel junctions

Magnetic tunnel junctions with the layer sequence Co$_2$Cr$_{0.6}$Fe$_{0.4}$Al/MgO/CoFe were fabricated by magnetron sputtering at room temperature (RT). The samples exhibit a large inverse tunneling magnetoresistance (TMR) effect of up to -66% at RT. The largest value of -84% at 20 K reflects a rather weak influence of temperature. The dependence on the voltage drop shows an unusual behavior with two almost symmetric peaks at $\pm600$ mV with large inverse TMR ratios and small positive values around zero bias

On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

Structural and magneto-transport characterization of Co_2Cr_xFe_(1-x)Al Heusler alloy films

We investigate the structure and magneto-transport properties of thin films of the Co_2Cr_xFe_(1-x)Al full-Heusler compound, which is predicted to be a half-metal by first-principles theoretical calculations. Thin films are deposited by magnetron sputtering at room temperature on various substrates in order to tune the growth from polycrystalline on thermally oxidized Si substrates to highly textured and even epitaxial on MgO(001) substrates, respectively. Our Heusler films are magnetically very soft and ferromagnetic with Curie temperatures up to 630 K. The total magnetic moment is reduced compared to the theoretical bulk value, but still comparable to values reported for films grown at elevated temperature. Polycrystalline Heusler films combined with MgO barriers are incorporated into magnetic tunnel junctions and yield 37% magnetoresistance at room temperature

Roofline-aware DVFS for GPUs

Graphics processing units (GPUs) are becoming increasingly popular for compute workloads, mainly because of their large number of processing elements and high-bandwidth to off-chip memory. The roofline model captures the ratio between the two (the compute-memory ratio), an important architectural parameter. This work proposes to change the compute-memory ratio dynamically, scaling the voltage and frequency (DVFS) of 1) memory for compute-intensive workloads and 2) processing elements for memory-intensive workloads. The result is an adaptive roofline-aware GPU that increases energy efficiency (up to 58%) while maintaining performance

A study of the potential of locality-aware thread scheduling for GPUs

Programming models such as CUDA and OpenCL allow the programmer to specify the independence of threads, effectively removing ordering constraints. Still, parallel architectures such as the graphics processing unit (GPU) do not exploit the potential of data-locality enabled by this independence. Therefore, programmers are required to manually perform data-locality optimisations such as memory coalescing or loop tiling. This work makes a case for locality-aware thread scheduling: re-ordering threads automatically for better locality to improve the programmability of multi-threaded processors. In particular, we analyse the potential of locality-aware thread scheduling for GPUs, considering among others cache performance, memory coalescing and bank locality. This work does not present an implementation of a locality-aware thread scheduler, but rather introduces the concept and identifies the potential. We conclude that non-optimised programs have the potential to achieve good cache and memory utilisation when using a smarter thread scheduler. A case-study of a naive matrix multiplication shows for example a 87% performance increase, leading to an IPC of 457 on a 512-core GPU