Wafer bonding solution to epitaxial graphene - silicon integration

The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphene nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing.Comment: 15 pages, 7 figure

Controlled epitaxial graphene growth within amorphous carbon corrals

Structured growth of high quality graphene is necessary for technological development of carbon based electronics. Specifically, control of the bunching and placement of surface steps under epitaxial graphene on SiC is an important consideration for graphene device production. We demonstrate lithographically patterned evaporated amorphous carbon corrals as a method to pin SiC surface steps. Evaporated amorphous carbon is an ideal step-flow barrier on SiC due to its chemical compatibility with graphene growth and its structural stability at high temperatures, as well as its patternability. The amorphous carbon is deposited in vacuum on SiC prior to graphene growth. In the graphene furnace at temperatures above 1200$^\circ$C, mobile SiC steps accumulate at these amorphous carbon barriers, forming an aligned step free region for graphene growth at temperatures above 1330$^\circ$C. AFM imaging and Raman spectroscopy support the formation of quality step-free graphene sheets grown on SiC with the step morphology aligned to the carbon grid

Structured epitaxial graphene: growth and properties

graphene ; nano-structure ; electronic transport ; ballistic transportInternational audienceGraphene is generally considered to be a strong candidate to succeed silicon as an electronic material. However, to date, it actually has not yet demonstrated capabilities that exceed standard semiconducting materials. Currently demonstrated viable graphene devices are essentially limited to micron size ultrahigh frequency analog field effect transistors and quantum Hall effect devices for metrology. Nanoscopically patterned graphene tends to have disordered edges which severely reduce mobilities thereby obviating its advantage over other materials. Here we show that graphene grown on structured silicon carbide surfaces overcomes the edge roughness and promises to provide an inroad into nanoscale patterning of graphene. We show that high quality ribbons and rings can be made using this technique. We also report on progress towards high mobility graphene monolayers on silicon carbide for device applications

Record Maximum Oscillation Frequency in C-face Epitaxial Graphene Transistors

The maximum oscillation frequency (fmax) quantifies the practical upper bound for useful circuit operation. We report here an fmax of 70 GHz in transistors using epitaxial graphene grown on the C-face of SiC. This is a significant improvement over Si-face epitaxial graphene used in the prior high frequency transistor studies, exemplifying the superior electronics potential of C-face epitaxial graphene. Careful transistor design using a high {\kappa} dielectric T-gate and self-aligned contacts, further contributed to the record-breaking fmax

Mono-layer C-face epitaxial graphene for high frequency electronics

As the thinnest material ever with high carrier mobility and saturation velocity, graphene is considered as a candidate for future high speed electronics. After pioneering research on graphene-based electronics at Georgia Tech, epitaxial graphene on SiC, along with other synthesized graphene, has been extensively investigated for possible applications in high frequency analog circuits. With a combined effort from academic and industrial research institutions, the best cut-off frequency of graphene radio-frequency (RF) transistors is already comparable to the best result of III-V material-based devices. However, the power gain performance of graphene transistors remained low, and the absence of a band gap inhibits the possibility of graphene in digital electronics. Aiming at solving these problems, this thesis will demonstrate the effort toward better high frequency power gain performance based on mono-layer epitaxial graphene on C-face SiC. Besides, a graphene/Si integration scheme will be proposed that utilizes the high speed potential of graphene electronics and logic functionality and maturity of Si-CMOS platform at the same time.Ph.D

Efficient Training of Large-Scale Industrial Fault Diagnostic Models through Federated Opportunistic Block Dropout

Artificial intelligence (AI)-empowered industrial fault diagnostics is important in ensuring the safe operation of industrial applications. Since complex industrial systems often involve multiple industrial plants (possibly belonging to different companies or subsidiaries) with sensitive data collected and stored in a distributed manner, collaborative fault diagnostic model training often needs to leverage federated learning (FL). As the scale of the industrial fault diagnostic models are often large and communication channels in such systems are often not exclusively used for FL model training, existing deployed FL model training frameworks cannot train such models efficiently across multiple institutions. In this paper, we report our experience developing and deploying the Federated Opportunistic Block Dropout (FedOBD) approach for industrial fault diagnostic model training. By decomposing large-scale models into semantic blocks and enabling FL participants to opportunistically upload selected important blocks in a quantized manner, it significantly reduces the communication overhead while maintaining model performance. Since its deployment in ENN Group in February 2022, FedOBD has served two coal chemical plants across two cities in China to build industrial fault prediction models. It helped the company reduce the training communication overhead by over 70% compared to its previous AI Engine, while maintaining model performance at over 85% test F1 score. To our knowledge, it is the first successfully deployed dropout-based FL approach

Epitaxial graphene on silicon carbide: Introduction to structured graphene

International audienceWe present an introduction to the rapidly growing field of epitaxial graphene on silicon carbide, tracing its development from the original proof-of-concept experiments a decade ago to its present, highly evolved state. The potential of epitaxial graphene as a new electronic material is now being recognized. Whether the ultimate promise of graphene-based electronics will ever be realized remains an open question. Silicon electronics is based on single-crystal substrates that allow reliable patterning on the nanoscale, which is an absolute requirement for any new electronic material. That is why epitaxial graphene is based on single-crystal silicon carbide. We also present recent results on nanopatterned graphene produced by etching the silicon carbide before annealing so that the graphene structures are produced in their final shapes. This avoids post annealing patterning, which is known to greatly affect transport properties on the nanoscale. Creating such structured graphene is an elegant method for avoiding pervasive patterning problems

Planar Edge Schottky Barrier-Tunneling Transistors Using Epitaxial Graphene/SiC Junctions

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