First-principles theoretical evaluation of crystalline zirconia and hafnia as gate oxides for Si microelectronics

Parameters determining the performance of the crystalline oxides zirconia (ZrO_2) and hafnia (HfO_2) as gate insulators in nanometric Si electronics are estimated via ab initio calculations of the energetics, dielectric properties, and band alignment of bulk and thin-film oxides on Si (001). With their large dielectric constants, stable and low-formation-energy interfaces, large valence offsets, and reasonable (though not optimal) conduction offsets (electron injection barriers), zirconia and hafnia appear to have a considerable potential as gate oxides for Si electronics.Comment: RevTeX 4 pages, 3 eps figure

Optical characterization of polysilazane based silica thin films on silicon substrates

In this work polysilazane based silica thin films grown on multilayer structures of different ultra-thin barriers (UTBs) on silicon substrates were studied. The silica thin films were obtained by polysilazane spin coating deposition (also called SOD, spin-on dielectrics) upon different UTB liners (silicon nitride or silicon dioxide). By curing the SOD with thermal treatments the polysilazane is converted into silica thin films. The degree of conversion to SiO2 was analyzed and the oxide local structure was studied in terms of Sisingle bondOsingle bondSi bridges by FTIR spectroscopy. Steady state and time resolved luminescence were applied to further characterize the oxide structure, the substrate–silica interfaces and the presence of defects. The analysis revealed the presence of dioxasilirane, double bond; length as m-dashSi(O2), and silylene, double bond; length as m-dashSi:, defect centers in the samples grown on silicon nitride UTB, while these defects are not observed in samples grown on silicon oxide UTB

Deposition temperature determination of HDPCVD silicon dioxide films

High density plasma chemical vapor deposition (HDPCVD) is a widely used technique in semiconductor integrated circuit (IC) manufacturing, especially to form inter-metal silicon (IMD) dioxide thin films. It was designed for commercially available tools in order to satisfy the gap filling requirements necessary for 0.18 and 0.15 mu m technology ICs, but it has been successfully extended also for 0.13 mu m technological node and over. HDPCVD technique has a potential impact on device electrical characteristics and metallurgy compatibility, according to process conditions, such as deposition temperature. The work here presented deals with some physical-chemical characteristics of the HDPCVD deposited thin undoped silicate glass (USG) films used in IC architecture. In a particular way, the dependence of the Si-OH bond concentration, revealed by FTIR, wet etch rate ratio compared with thermal SiO2 and hydrogen content, determined by elastic recoil detection analysis (ERDA), are correlated with deposition temperature. The results demonstrate how it is possible after film deposition to reveal from the HDPCVD USG film itself which real temperature it has been deposited at, allowing a practical method in production environment for statistical process control

Mechanical stress in silicon nanosized architectures: Defects of SOD processed silica filler

The mechanical stress in nanosized silicon architectures is studied in shallow trench isolation systems with different liners and spin on dielectrics processed silica filler by means of Raman spectroscopy. The nanopatterning of silicon wafers causes a tensile stress of the system whereas the presence of the filler induces a compressive stress which depends on the interaction between silica filler and liner: by changing the liner from silicon dioxide to silicon nitride one can induce a larger compressive stress. The analysis of the ultraviolet excited emission properties in the visible range (nanosecond lasting bands at 2.5, 3.0 and 3.3 eV) allowed us to individuate and locate silica related defects and to correlate their presence to the induced compressive stress