DTLS Performance in Duty-Cycled Networks

The Datagram Transport Layer Security (DTLS) protocol is the IETF standard for securing the Internet of Things. The Constrained Application Protocol, ZigBee IP, and Lightweight Machine-to-Machine (LWM2M) mandate its use for securing application traffic. There has been much debate in both the standardization and research communities on the applicability of DTLS to constrained environments. The main concerns are the communication overhead and latency of the DTLS handshake, and the memory footprint of a DTLS implementation. This paper provides a thorough performance evaluation of DTLS in different duty-cycled networks through real-world experimentation, emulation and analysis. In particular, we measure the duration of the DTLS handshake when using three duty cycling link-layer protocols: preamble-sampling, the IEEE 802.15.4 beacon-enabled mode and the IEEE 802.15.4e Time Slotted Channel Hopping mode. The reported results demonstrate surprisingly poor performance of DTLS in radio duty-cycled networks. Because a DTLS client and a server exchange more than 10 signaling packets, the DTLS handshake takes between a handful of seconds and several tens of seconds, with similar results for different duty cycling protocols. Moreover, because of their limited memory, typical constrained nodes can only maintain 3-5 simultaneous DTLS sessions, which highlights the need for using DTLS parsimoniously.Comment: International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC - 2015), IEEE, IEEE, 2015, http://pimrc2015.eee.hku.hk/index.htm

Sustainable Traffic Aware Duty-Cycle Adaptation in Harvested Multi-Hop Wireless Sensor Networks

International audienceSustainable power management techniques in energy harvesting wireless sensors currently adapt the consumption of sensors to their harvesting rate within the limits of their battery residual energy, but regardless of the traffic profile. To provide a fairer distribution of the energy according to application needs, we propose a new sustainable traffic aware duty-cycle adaptation scheme (STADA) that takes into account the traffic load in addition to previous factors. We evaluate our protocol in the specific context of multi-hop IEEE 802.15.4 beacon-enabled wireless sensor networks powered by solar energy. Simulations show that our solution outperforms traffic-unaware adaptation schemes while minimizing the variance of the quality of service provided to applications

Energy Consumption and Performance of IEEE 802.15.4e TSCH and DSME

International audienceThe recent IEEE 802.15.4e standard has introduced two interesting modes of operation: Time Slotted Channel Hopping (TSCH) and Deterministic and Synchronous Multi-channel Extension (DSME). Both provide a mix of time and frequency division to improve the performance of the previously available synchronized MAC mode (beacon-enabled 802.15.4). In this paper, we compare the performance of DSME and TSCH with respect to the energy consumption, throughput, and delay through an analysis of their respective ways of operation. We use an energy consumption model coming from our previous experience on the design of recent energy harvesting motes for the GreenNet platform. Our results show that DSME performs slightly better in terms of the energy consumption spent in data transfers. Both protocols exhibit similar delays for a given duty cycle, nevertheless, TSCH obtains shorter delay and higher throughput for low duty cycles. For higher duty cycles, TSCH results in lower throughput—for applications that send little data, the fixed slot configuration of TSCH results in wasted bandwidth. DSME can allocate shorter slots, which is beneficial for applications that transmit short packets

DTLS Performance in Duty-Cycled Networks

International audienceThe Datagram Transport Layer Security (DTLS) protocol is the IETF standard for securing the Internet of Things. The Constrained Application Protocol, ZigBee IP, and Lightweight Machine-to-Machine (LWM2M) mandate its use for securing application traffic. There has been much debate in both the standardization and research communities on the applicability of DTLS to constrained environments. The main concerns are the communication overhead and latency of the DTLS handshake, and the memory footprint of a DTLS implementation. This paper provides a thorough performance evaluation of DTLS in different duty-cycled networks through real-world experimentation, emulation and analysis. In particular, we measure the duration of the DTLS handshake when using three duty cycling link-layer protocols: preamble-sampling, the IEEE 802.15.4 beacon-enabled mode and the IEEE 802.15.4e Time Slotted Channel Hopping mode. The reported results demonstrate surprisingly poor performance of DTLS in radio duty-cycled networks. Because a DTLS client and a server exchange more than 10 signaling packets, the DTLS handshake takes between a handful of seconds and several tens of seconds, with similar results for different duty cycling protocols. Moreover, because of their limited memory, typical constrained nodes can only maintain 3-5 simultaneous DTLS sessions, which highlights the need for using DTLS parsimoniously

Mass testing of the JUNO experiment 20-inch PMTs readout electronics

The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose, large size, liquid scintillator experiment under construction in China. JUNO will perform leading measurements detecting neutrinos from different sources (reactor, terrestrial and astrophysical neutrinos) covering a wide energy range (from 200 keV to several GeV). This paper focuses on the design and development of a test protocol for the 20-inch PMT underwater readout electronics, performed in parallel to the mass production line. In a time period of about ten months, a total number of 6950 electronic boards were tested with an acceptance yield of 99.1%

Implementation and performances of the IPbus protocol for the JUNO Large-PMT readout electronics

The Jiangmen Underground Neutrino Observatory (JUNO) is a large neutrino detector currently under construction in China. Thanks to the tight requirements on its optical and radio-purity properties, it will be able to perform leading measurements detecting terrestrial and astrophysical neutrinos in a wide energy range from tens of keV to hundreds of MeV. A key requirement for the success of the experiment is an unprecedented 3% energy resolution, guaranteed by its large active mass (20 kton) and the use of more than 20,000 20-inch photo-multiplier tubes (PMTs) acquired by high-speed, high-resolution sampling electronics located very close to the PMTs. As the Front-End and Read-Out electronics is expected to continuously run underwater for 30 years, a reliable readout acquisition system capable of handling the timestamped data stream coming from the Large-PMTs and permitting to simultaneously monitor and operate remotely the inaccessible electronics had to be developed. In this contribution, the firmware and hardware implementation of the IPbus based readout protocol will be presented, together with the performances measured on final modules during the mass production of the electronics

Validation and integration tests of the JUNO 20-inch PMTs readout electronics

The Jiangmen Underground Neutrino Observatory (JUNO) is a large neutrino detector currently under construction in China. JUNO will be able to study the neutrino mass ordering and to perform leading measurements detecting terrestrial and astrophysical neutrinos in a wide energy range, spanning from 200 keV to several GeV. Given the ambitious physics goals of JUNO, the electronic system has to meet specific tight requirements, and a thorough characterization is required. The present paper describes the tests performed on the readout modules to measure their performances.Comment: 20 pages, 13 figure

Exploration de l'espace des architectures mémoire pour des systèmes de traitement d'image avec références non affines aux données (application à des blocs fondamentaux d'un modèle de rétine numérique)

Dans le cadre de la synthèse de haut niveau (SHN), qui permet d extraire un modèle structural à partir d un modèle algorithmique, nous proposons des solutions pour optimiser l accès et le transfert de données du matériel cible. Une méthodologie d exploration de l espace des architectures mémoire possibles a été mise au point. Cette méthodologie trouve un compromis entre la quantité de mémoire interne utilisée et les performances temporelles du matériel généré. Deux niveau d optimisation existe : 1)Une optimisation architecturale, qui consiste à créer une hiérarchie mémoire, 2)Une optimisation algorithmique, qui consiste à partitionner la totalité des données manipulées pour stocker en interne seulement celles qui sont utiles dans l immédiat. Pour chaque répartition possible, nous résolvonsle problème de l ordonnancement des calculs et de mapping des données. À la fin, nous choisissons la ou les solutions pareto. Nous proposons un outil, front-end de la SHN, qui est capable d appliquer l optimisation algorithmique du point 2) à un algorithme de traitement d image spécifié par l utilisateur. L outil produit en sortie un modèle algorithmique optimisé pour la SHN, en customisant une architecture générique.The aim of this Phd is to propose a methodology that improves the data transfer and management for applications having non-affine arra references.The target applications are iterative image processing algorithms which are non-recursive and have static dependences. These applications are weil described by a Joop based C-code and they can undergo a High Level Synthesis which in fer a RTL model from an input C-code. The input code of the HLS can be optimized, by the loop transformations, with respect to its data storage and management.ln fact, in the trame of polyhedral model, the loop transformations enhance data locality and allow the computation parallelism and the data prefetchin. These transformations require that the array references are affine.ln our model we proposes a method to apply data and operations partitionning for applications with non-affine array references. An exploration is run with different tiling of input and output data spaces. The output tiling is than projected onto the input tiling. The outpu tiles calculations are re-schedulied in order to minimize the internai memory or optimize the temporal performance of the produced system. A mapping between the input tiles and the internai buffers is computed and, at the end, the best solutions in the analyzed set are chosen.GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

Mexp, a front-end tool for hls of image processing applications

International audienc

DataJoin: An Energy-Efficient Joining Scheme for 802.15.4e TSCH Networks

International audienc