Output-based assessment of herd-level freedom from infection in endemic situations:Application of a Bayesian Hidden Markov model

International audienceCountries have implemented control programmes (CPs) for cattle diseases such as bovine viral diarrhoea virus (BVDV) that are tailored to each country-specific situation. Practical methods are needed to assess the output of these CPs in terms of the confidence of freedom from infection that is achieved. As part of the STOC free project, a Bayesian Hidden Markov model was developed, called STOC free model, to estimate the probability of infection at herd-level. In the current study, the STOC free model was applied to BVDV field data in four study regions, from CPs based on ear notch samples. The aim of this study was to estimate the probability of herd-level freedom from BVDV in regions that are not (yet) free. We additionally evaluated the sensitivity of the parameter estimates and predicted probabilities of freedom to the prior distributions for the different model parameters. First, default priors were used in the model to enable comparison of model outputs between study regions. Thereafter, country-specific priors based on expert opinion or historical data were used in the model, to study the influence of the priors on the results and to obtain country-specific estimates.The STOC free model calculates a posterior value for the model parameters (e.g. herd-level test sensitivity and specificity, probability of introduction of infection) and a predicted probability of infection. The probability of freedom from infection was computed as one minus the probability of infection. For dairy herds that were considered free from infection within their own CP, the predicted probabilities of freedom were very high for all study regions ranging from 0.98 to 1.00, regardless of the use of default or country-specific priors. The priors did have more influence on two of the model parameters, herd-level sensitivity and the probability of remaining infected, due to the low prevalence and incidence of BVDV in the study regions. The advantage of STOC free model compared to scenario tree modelling, the reference method, is that actual data from the CP can be used and estimates are easily updated when new data becomes availabl

A framework for assessing confidence in freedom from infection in animal disease control programmes

In the Surveillance Tool for Outcome-based Comparison of FREEdom from infection (STOC free) project (https://www.stocfree.eu), a data collection tool was constructed to facilitate standardised collection of input data, and a model was developed to allow a standardised and harmonised comparison of the outputs of different control programmes (CPs) for cattle diseases. The STOC free model can be used to evaluate the probability of freedom from infection for herds in CPs and to determine whether these CPs comply with the European Union's pre-defined output-based standards. Bovine viral diarrhoea virus (BVDV) was chosen as the case disease for this project because of the diversity in CPs in the six participating countries. Detailed BVDV CP and risk factor information was collected using the data collection tool. For inclusion of the data in the STOC free model, key aspects and default values were quantified. A Bayesian hidden Markov model was deemed appropriate, and a model was developed for BVDV CPs. The model was tested and validated using real BVDV CP data from partner countries, and corresponding computer code was made publicly available. The STOC free model focuses on herd-level data, although that animal-level data can be included after aggregation to herd level. The STOC free model is applicable to diseases that are endemic, given that it needs the presence of some infection to estimate parameters and enable convergence. In countries where infection-free status has been achieved, a scenario tree model could be a better suited tool. Further work is recommended to generalise the STOC free model to other diseases

A living lab approach to understanding dairy farmers' needs of technologies and data to improve herd health: Focus groups from 6 European countries

For successful development and adoption of technology on dairy farms, farmers need to be included in the innovation process. However, the design of agricultural technologies usually takes a top-down approach with little involvement of end-users at the early stages. Living Labs offer a methodology that involve end-users throughout the development process and emphasize the importance of understanding users' needs. Currently, exploration of dairy farmers' needs of technologies has been limited to specific types of technology (e.g., smartphone apps) and adult cattle. The aim of this study was to use a Living Lab approach to identify dairy farmers' needs of data and technologies to improve herd health and inform innovation development. Eighteen focus groups were conducted with, in total, 80 dairy farmers from Belgium, Ireland, the Netherlands, Norway, Sweden, and the UK. Data were analyzed using Template Analysis and 6 themes were generated which represented the fundamental needs of autonomy, comfort, competence, community and relatedness, purpose, and security. Farmers favored technologies that provided them with convenience, facilitated their knowledge and understanding of problems on farm, and allowed them to be self-reliant. Issues with data sharing and accessibility, and usability of software were barriers to technology use. Furthermore, farmers were facing problems around recruitment and management of labor and needed ways to reduce stress. Controlling aspects of the barn environment, such as air quality, hygiene, and stocking density, was a particular concern in relation to youngstock management. In conclusion, the findings suggest that developers of farm technologies may want to include farmers in the design process to ensure a positive user experience and improve accessibility. The needs identified in this study can be used as a framework when designing farm technologies to strengthen need satisfaction and reduce any potential harm toward needs

Towards standardization of compact data center switches

Data Centers, the essential infrastructure for the increasing amount of cloud applications, are required to expand in number of devices even further. However, the scaling is limited by both space and power constraints. It is therefore essential to shrink the size and power consumption of the devices. This works explores how On-Board Optics provides a solution for data center switches. We experimentally demonstrate a proof-of-concept data center switch with integrated On-Board Optics modules, power consumption below 150W and measuring only 0.25U. We further discuss the standards required to fully exploit this technology, and the future of On-Board Optics

Hybrid fat-tree:extending fat-tree to exploit optical switch transparency with WDM

\u3cp\u3eData center networks are the underlying infrastructure supporting the exponential growth of cloud services. Several data center network architectures based on electronic switches or on a combination of electronic and optical switches have been suggested in order to cope with ever-increasing demands. However, a common analytic model describing the network architectures in terms of servers, switches, transceivers, and fibers is lacking. Hence, a true comparison of the scaling in power consumption and cost between different topologies is difficult. This work presents a mathematical framework defining electronic and hybrid topologies under the same model parameters. It explores how the introduction of wavelength-division multiplexing (WDM) and optical switches in Fat-Tree like topologies impact their scaling. We find that these technologies reduce the required number of switches by 45%, transceivers by 60%, and fibers by 50% in the minimum hybrid networks. In such networks, our real case scenario study based on 25G technologies available at present predicts power savings of at least 55% and cost savings of at least 48%. On top of that, larger savings are foreseen when increased port-density transceivers become available.\u3c/p\u3

A novel scalable and low latency hybrid data center network architecture based on flow controlled fast optical switches

\u3cp\u3eWe present a novel hybrid DCN based on flow-controlled fast optical switches. Results show packet loss <1.4E-5 and latency <2.4μs for 100,000 servers (0.3 load). Costs and power consumptions are also compared with current technologies.\u3c/p\u3

48×10 Gbps cost-effective FPC-based on-board optical transmitter with PGA connector

High bandwidth density on-board optical transmitter is reported in this paper. This on-board transmitter contains 4×12-channel 10Gbps CMOS driver ICs and 4×12-channel 850nm Multimode (MM) VCSEL arrays, with a total 48×10Gbps bandwidth and is packaged through flip-chip bonding on a flexible printed circuit (FPC) with SnAg solder bumps. Due to the compact package design, based on a commercial 1mm pitch ISI HoLi pin grid array (PGA) connector, the size of FPC is only 31.5mm × 31.5mm and it offers a state-of-art bandwidth density of 0.483Gbps/mm2. Investigation of RF signal propagation on the FPC is carried out for design validation at 10Gbps and to further explore the potential of the suggested platform differential pairs are simulated up to 30Gbps. An optical straight lens connector is used to couple the light to a single 48 fibers MT connector. To validate the design concept the fully assembled transmitter is tested at 10Gbps. Bit error rates for all 48 channels at 10Gbps as well as eye diagrams for few representative channels are reported

Chip scale 12-channel 10 Gb/s optical transmitter and receiver subassemblies based on wet etched silicon interposer

\u3cp\u3eIn this paper, compact optical subassemblies are demonstrated based on a novel silicon interposer, which is designed and fabricated in a wafer scale process. The interposer includes the design of optical and electrical connections. A low-cost fabrication method, wet etching, is used to define light inputs and outputs as well as create the required recesses in the interposer to embed the chips into the silicon wafer at the same time. Impedance matched traces, for the high speed signals of the CMOS and opto-electronic ICs, are designed using advanced design system software and transferred onto the interposer by photolithography and electro-plating, which are accomplished on the deeply etched topology. The whole process flow of the silicon interposer patterning is designed and demonstrated, and the challenges are discussed. After the process, the optoelectronic dies and their complimentary CMOS parts are flipped and bonded on the interposer in close proximity, and a mechanical optical interface (MOI) is mounted for light coupling. Both transmitter and receiver subassemblies provide 12 parallel optical interconnections, and are scaled down to an area measuring 6 by 8 mm. Signal integrity testing is performed on a probe station for 10 Gb/s data signal delivering clear eye patterns for all channels (in both Rx and Tx subassemblies). The performance is further characterized using bit error rate (BER) testing. Both transmitter and receiver assemblies outperform a reference SFP+, with receiver sensitivity of-10 dBm at a BER lower than 10\u3csup\u3e-12\u3c/sup\u3e after compensating for the MOI insertion loss. Finally, we also test the assemblies for crosstalk and demonstrate that the current design has a maximal additional penalty lower than 0.2 and 0.8 dB for transmitter and receiver, respectively.\u3c/p\u3