Apparatus and method for chip-scale package with capacitors as bumps

A method and apparatus relating to chip-scale packaging is provided. According to an embodiment of the invention electrical solder bump interconnection between an integrated circuit package and a substrate is replaced by the placement and attachment of discrete SMD components between pads on the integrated circuit and substrate. Said substrate being for example a low-temperature co-fired ceramic such as alumina or a PCB such as FR4. Accordingly discrete SMD capacitors, inductors etc can be packaged with the system design goals of minimizing board real-estate, enhancing performance, and cost addressed in a novel manner without requiring substantial development of new processes by manufacturers. The embodiments of the invention minimizing the parasitic series impedance of decoupling capacitor connections for example whilst allowing a small-form-factor System-in-Package to be realized

Through-substrate via and redistribution layer with metal paste

The invention relates to a semiconductor device for use in a stacked configuration of the semiconductor device and a further semiconductor device. The semiconductor device comprises: a substrate (5) comprising at least part of an electronic circuit (7) provided at a first side thereof. The substrate (5) comprises a passivation layer (19) at the first side and a substrate via that extends from the first side to a via depth beyond a depth of the electronic circuit (7) such that it is reconfigurable into a through-substrate via (10) by backside thinning of the substrate (5). The semiconductor device further comprises: a patterned masking layer (15) on the first side of the substrate (5). The patterned masking layer (15) comprises at least a trench (16) extending fully through the patterned masking layer (15). The trench has been filled with a redistribution conductor (20). The substrate via and the redistribution conductor (20) comprise metal paste (MP) and together form one piece. The effect of the features of the semiconductor device of the inventionis that there is no physical interface between those the through-substrate via (10) and the redistribution conductor (20). As a consequence of the invention the parasitic resistance of this electrical connection is reduced, which results in a better electrical performance of the semiconductor device. The invention further relates to a method of manufacturing such semiconductor device. And the invention relates to a semiconductor assembly comprising a stacked configuration of a plurality of such semiconductor devices

Through-substrate via and redistribution layer with metal paste

A semiconductor device and a method for manufacturing such semiconductor device for use in a stacked configuration of the semiconductor device are disclosed. The semiconductor device includes a substrate including at least part of an electronic circuit provided at a first side thereof. The substrate includes a passivation layer and a substrate via that extends from the first side to a via depth such that it is reconfigurable into a through-substrate. The semiconductor device further includes a patterned masking layer on the first side of the substrate. The patterned masking layer includes a trench extending fully through the patterned masking layer. The trench has been filled with a redistribution conductor.; The substrate via and the redistribution conductor include metal paste and together form one piece, such that there is no physical interface between the through-substrate via and the redistribution conductor. Thus, the parasitic resistance of this electrical connection is reduced