Verification of a frequency dispersion modelin the performance of a GaAs pHEMT travelling-wave MMIC

The impact of frequency dispersive effects on typical figures of merit is investigated in a distributed MMIC realized in 0.15µm GaAs pHEMT technology. A novel compact dispersion model, allowing for accurate simulation of both static and dynamic multiple time constant IV characteristics, is employed. In a comparison of measurement and simulation, the model is both validated and used to quantify and interpret the error introduced when neglecting frequency dispersion in the design of MMICs. Device operation is investigated with respect to gain, linearity and power-added efficiency,all of them affected by dispersion effects. The model is shown to significantly improve simulation accuracy by increasing the validity range in terms of the frequency-and voltage regimes

Coplanar W-Band Low Noise Amplifier NMIC Using 100-nm Gate-length GaAs PHEMTs

This paper presents the performance of a W-band low noise amplifier MMIC, based on coplanar technology, and utilizing 100-nm gate-length GaAs pseudomorphic power HEMTs. With a chip size of less than 2 mm2, this two-stage LNA achieves a small signal gain of more than 12 dB between 90 and 100 GHz, with 12.5-dB gain and 3.9-dB noise figure at 94 GHz. This is the best reported performance for power PHEMT-based LNAs at W-band, which is also comparable to the best results reported with more advanced InP or Metamorphic HEMT low noise technologies

Study of the influence of gate etching and passivation on current dispersion, trapping and reliability in RF 0.15 mu m AlGaN/GaN HEMTs

In this paper we examine the effect of passivation and gate etching processes on the current dispersion and reli-ability of AlGaN/GaN HEMTs for RF applications. We compared the performance of HEMTs with a standard gate etching and passivation processes (reference wafer) with the performances of HEMTs with improved etching process (etching variant wafer) and improved passivation process (passivation variant wafer). In order to study the trapping behavior, we performed dispersion measurements in off-state conditions and drain current tran-sients (DCT) and we found that: 1) The use of improved passivation process determines a decrease of current dispersion, in particular at the knee voltage, where current collapse depends on both threshold voltage and on-resistance variation, 2) The trapping process linked to surface states is influenced by the gate etching and passivation processes; the use of improved passivation slows down the trapping/de-trapping kinetics, resulting in a lower impact on dynamic performance. The study of reliability is based on high-temperature reverse bias (HTRB) stresses. The gate-drain diodes are biased in the same voltage stress conditions (VGS,Stress =-7 V, VDS,Stress = 50 V) at high temperatures (175 degrees C) for 24 h. We demonstrated that the improved passivation limits the increase of gate leakage current during HTRB stress and prevents the belly shape effect linked to the presence of donor traps in the surface between SiN and GaN cap. We performed gate step stress increasing the negative voltage applied to the Schottky contact. The electro-luminescence images performed during the stress show spots along the gate finger that are the responsible of the failure of the devices. The results presented in the paper provide information on the optimization of GaN HEMTs for RF applications

Transconductance Overshoot, a New Trap-Related Effect in AlGaN/GaN HEMTs

DC characteristics of AlGaN/GaN HEMTs with different thickness values of the undoped GaN channel layer were compared. An abnormal transconductance (gm) overshoot accompanied by a negative threshold voltage (V-TH) shift was observed during IDS-V-GS sweep in devices with thinner GaN layer. At the same time, a non-monotonic increase in gate current was observed. In OFF-state, electron trapping occurs in the undoped GaN layer or at the GaN/AlN interface, leading to a positive VTH shift. When the device is turning on at a sufficiently high V-DS, electron de-trapping occurs due to trap impact-ionization; consequently, V-TH and therefore ID suddenly recovers, leading to the gm overshoot effect. These effects are attributed to electron trap impact-ionization and consequent modulation of the device's electric field

Impact of an AlGaN spike in the buffer in 0.15 μm AlGaN/GaN HEMTs during step stress

On-wafer robustness and short-term reliability of 0.15 μm AlGaN/GaN HEMTs, fabricated on AlGaN buffer with a ‘mono-layer’ and c backbarrier between channel and buffer layers, have been compared. Results of DC characterization showed that devices with AlGaN ‘bi-layer’ backbarrier have better subthreshold behaviour, reduced on-resistance and leakage current, together with a slightly lower current and transconductance. Electroluminescence measurements suggested an increase of electric field in the ‘bi-layer’ devices. Observed failure modes are the following: (a) during off-state stress, threshold voltage shifts towards more negative values; (b) for semi-on and on-state tests, a non-monotonic threshold voltage instability, which initially becomes negative and then recovers is common to both types of devices; (c) during semi-on and on-state tests, a significant increase of RON occurs, which seems to be faster in devices without spike, despite the lower electric field suggested by EL measurements. Degradation of electrical characteristics has been attributed to the instability of charge on Carbon-related acceptor levels, enhanced by hot-electron effects

On-Wafer Fast Evaluation of Failure Mechanism of 0.25-μm AlGaN/GaN HEMTs: Evidence of Sidewall Indiffusion

In this article, we present the results of on-wafer short-term (24 h) stress tests carried out on 0.25- μm AlGaN/GaN HEMTs. Devices on-wafer were submitted to 24-h dc tests, at various gate and drain voltage values corresponding to dissipated power densities PD up to 40 W/mm, with estimated channel temperature 375 °C. GEN1 devices adopted a Ni/Pt/Au gate metallization and conventional plasma-enhanced chemical vapor deposition (PE-CVD) SiN passivation; in GEN2 devices, a modified gate metallization and a two-layer SiN passivation were adopted. When tested at Pd >25 W/mm, a substantial decrease of drain current ID and transconductance gm was measured in GEN1 HEMTs, without any significant shift of threshold voltage. Failure analysis revealed that Au and O interdiffusion took place from the sidewalls; Au gradually substituted Ni as a Schottky contact, while O, in the presence of high electric field, high temperature, and high current, promoted (Al)GaN oxidation and pitting. On the contrary, negligible degradation was found after high temperature storage of GEN1 devices without applied bias, up to 450 °C. In GEN2, process modification was effective in reducing the impact of this failure mechanism, resulting in only 5% gm decrease after 24 h at a junction temperature of 375 °C with PD = 38 W/mm. Results demonstrate the effectiveness of the adopted on-wafer screening methodology in identifying potentially dangerous failure mechanisms