3 research outputs found

    MoS<sub>2</sub> Transistors Fabricated <i>via</i> Plasma-Assisted Nanoprinting of Few-Layer MoS<sub>2</sub> Flakes into Large-Area Arrays

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    Large-area few-layer-MoS<sub>2</sub> device arrays are desirable for scale-up applications in nanoelectronics. Here we present a novel approach for producing orderly arranged, pristine few-layer MoS<sub>2</sub> flakes, which holds significant potential to be developed into a nanomanufacturing technology that can be scaled up. We pattern bulk MoS<sub>2</sub> stamps using lithographic techniques and subsequently transfer-print prepatterned MoS<sub>2</sub> features onto pristine and plasma-charged SiO<sub>2</sub> substrates. Our work successfully demonstrates the transfer printing of MoS<sub>2</sub> flakes into ordered arrays over cm<sup>2</sup>-scale areas. Especially, the MoS<sub>2</sub> patterns printed on plasma-charged substrates feature a regular edge profile and a narrow distribution of MoS<sub>2</sub> flake thicknesses (<i>i</i>.<i>e</i>., 3.0 ± 1.9 nm) over cm<sup>2</sup>-scale areas. Furthermore, we experimentally show that our plasma-assisted printing process can be generally used for producing other emerging atomically layered nanostructures (<i>e</i>.<i>g</i>., graphene nanoribbons). We also demonstrate working n-type transistors made from printed MoS<sub>2</sub> flakes that exhibit excellent properties (<i>e</i>.<i>g</i>., ON/OFF current ratio 10<sup>5</sup>–10<sup>7</sup>, field-effect mobility on SiO<sub>2</sub> gate dielectrics 6 to 44 cm<sup>2</sup>/(V s)) as well as good uniformity of such transistor parameters over a large area. Finally, with additional plasma treatment processes, we also show the feasibility of creation of p-type transistors as well as pn junctions in MoS<sub>2</sub> flakes. This work lays an important foundation for future scale-up nanoelectronic applications of few-layer-MoS<sub>2</sub> micro- and nanostructures
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