Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL

Reconstruction 3D temps réel dans un VSIP

- Dans cet article sont décrits un système intégré pour la reconstruction du relief, les contraintes et les choix de conception, la structure du capteur de vision active et les méthodes et architectures utilisées pour obtenir une représentation 3D en temps réel

Studying Potential Side Channel Leakages on an Embedded Biometric Comparison System

We study in this work the potential side channel leakages of a hardware biometric comparison system that has been designed for fingerprints. An embedded biometric system for comparison aims at comparing a stored biometric data with a freshly acquired one without the need to send the stored biometric data outside the system. Here one may try to retrieve the stored data via side channel, similarly as for embedded cryptographic modules where one may try to exploit side channel for attacking the modules. On one hand, we show that we can find partial information by the means of simple Side Channel Analysis that may help to retrieve the stored fingerprint. On the other hand, we illustrate that reconstructing the fingerprint remains not trivial and we give some simple countermeasures to protect further the comparison algorithm

Etude d'une architecture de traitement pour un capteur intégré de vision 3D

Cette thèse porte sur l'étude d'une architecture pour la vision en 3D dans un capteur intégré. L'évolution des technologies et de la densité d'intégration des circuits électroniques permet d'envisager de nouveaux systèmes intégrés capables de réaliser l'acquisition, le traitement et la transmission de données. Grâce à cette évolution nous avons envisagé la réalisation d'un capteur actif de vision 3D intégré. Ce capteur de vision active a pour fonction la restitution du relief en repoussant les limites des systèmes existants. Ceci permet d'entrevoir de nouvelles applications où la taille, la précision, les temps de traitement ou la consommation électrique sont des contraintes fortes. Nous proposons dans ce manuscrit, la structure globale du capteur, une méthode pour la reconstruction du relief, une architecture pour une exécution efficace de cette méthode ainsi que la réalisation d'un démonstrateur permettant de valider expérimentalement les concepts présentés.This thesis relates to the study of an architecture for active 3D vision in an integrated sensor. Electronic circuits technology evolution and the integration level growth allows the design of new integrated systems able to acquire, process and transmit data. This led us to consider the design of an integrated active 3D vision sensor. This sensor overcomes the limitations of the existing systems and thus, allows the emergence of new applications where size, precision, processing times or power consumption are strong constraints . In this manuscript, we have proposed a global scheme for the sensor, a method for depth reconstruction and a processing architecture. We have also presented the realization of a prototype to validate experimentally the presented concepts.PARIS-BIUSJ-Thèses (751052125) / SudocPARIS-BIUSJ-Physique recherche (751052113) / SudocSudocFranceF

Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology

<p>In this paper we present quaternary and ternary routing tracks for FPGAs, and their implementation in 28nm FDSOI technology. We discuss the transistor level design of multi-valued repeaters, multiplexers and translators, and specific features of FDSOI technology which make it possible. Next we compare the multi-valued routing architectures with equivalent single driver two-valued routing architectures. We show that for long tracks, it is possible to achieve upto 3x reduction in dynamic switching energy, upto 2x reduction in routing wire area and 10% reduction in area dedicated to routing resources. The multi-valued tracks are slightly more susceptible to process variation. We present a layout method for multivalued standard cells and determine the layout overhead.We conclude with various usage scenarios of these tracks.</p

Multi-Level Formal Analysis, A New Direction for Fault Injection Attack?

International audience<p>Fault injection attack is an extremely pow-erful technique to extract secrets from an embeddedsystem. Since their introduction, a large number ofcountermeasures have been proposed. Unfortunately,they suffer from two major drawbacks: a very high coston system performance, and a security frequently ques-tioned. The first point can be explained by their design,based on techniques from Reliability domain, which re-sult in solutions protecting against fault models eitherhighly improbable in a context of attack, or that donot permit secret extraction. At the opposite, the sec-ond point is due to the use of an incomplete attackermodel for the security evaluation at design step. In thispaper, we propose a new approach: multi-level formalverification, based on models encompassing the capabil-ities of the attacker, the susceptibility to faults of thehardware platform hosting the implementation, and theconstraints imposed by the algorithm used for secretextraction. We first explain that the success of a faultinjection attack depends solely on races between signals,which can be analyzed automatically. Then, we performa multi-level evaluation on a hardware implementationof AES-128, which shows that the overhead of a coun-termeasure can be divided by eight while maintainingan almost identical level of security. Finally, we extendthe model to electromagnetic injection.</p

Stochastic model of a Metastability-based True Random Number Generator

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A digital processing architecture for 3D reconstruction

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Stereo Vision

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