A wideband supply modulator for 20MHz RF bandwidth polar PAs in 65nm CMOS

A wideband modulator for a 20MHz bandwidth polar modulated PA is presented which achieves a maximum efficiency of 87.5% and a small signal -3dB bandwidth of 285MHz. Realized in 65nm CMOS, it consists of a cascoded nested Miller compensated linear amplifier and a class D switching amplifier. It can deliver 22.7dBm output power to a 5.3Ω load. With a switching frequency of 118MHz, the output switching ripple is 4.3mVrms. Keywords: supply modulator, power amplifier, CMOS and cascoded nested Miller

Wideband cancellation of second order intermodulation distortions in a 60-GHz zero-IF mixer

The 1GHz target IF bandwidth of 60GHz zero-IF mixers makes conventional single- and double-parameter tuning methods ineffective for suppression of second-order intermodulation distortions across the whole IF band. In this paper a three-dimensional circuit parameter tuning method is used to address this problem. Output resistance, output capacitance, and gate biasing of the switching pairs are three parameters chosen for tuning. The mixer is designed and fabricated in CMOS 45nm technology. Measurement results show that the IMD2 tones across the whole 1GHz IF band can be suppressed simultaneously to within the noise level. The measured power conversion gain, IIP3 and typical corrected IIP2 of the mixer are 7dB, -7dBm and 27dBm, respectively

A 60GHz Digitally Controlled RF-Beamforming Receiver Front-end in 65nm CMOS

http://alexandria.tue.nl/campusonly/Metis223347.pdfPhased arrays form a crucial step towards high data rate 60GHz wireless communication. This paper presents a fully integrated digitally controlled 60GHz RF-beamforming receiver front-end in CMOS. Using digitally controlled active phase shifters, each path of the scalable architecture achieves 10dB power gain, 7.2dB noise figure, a 360º phase shift range in 22.5º steps at 61GHz, and a 3dB-bandwidth of 5.4GHz, while only dissipating 78mW in each path. Chip area is 1.6mm2

A 60GHz Miller effect based VCO in 65nm CMOS with 10.5% tuning range

This paper presents a 60 GHz voltage controlled oscillator implemented in conventional 65 nm CMOS technology. This VCO employs an alternative tuning system based on the Miller capacitance instead of conventional varactors. The presented VCO has a tuning range of 10.5 % and operates in the frequency range of 59.5 GHz to 66.1 GHz. It has an output power of -13 dBm and a phase noise of 80 dBc to -85 dBc/Hz @ 1 MHz over its entire range. The figure-of-merit (FOM) of this VCO is -162 dB

MEMS-based reconfigurable multi-band BiCMOS power amplifier

This paper presents a small dual-band 0.9GHz/1.8GHz inverse class F power amplifier with load-switch functionality using a single BiCMOS amplifier line-up with a MEMS based reconfigurable matching network. The realized prototype measures 40mm2, offers 31dBm with 40% efficiency at 0.9GHz and 30dBm with 34% at 1.8GHz. The load-switch provides up to 10% efficiency improvement at 0.9GHz for reduced power level

MEMS-Based Reconfigurable Multi-band BiCMOS Power Amplifier

This paper presents a small dual-band 0.9GHz/1.8GHz inverse class F power amplifier with load-switch functionality using a single BiCMOS amplifier line-up with a MEMS based reconfigurable matching network. The realized prototype measures 40mm2, offers 31dBm with 40% efficiency at 0.9GHz and 30dBm with 34% at 1.8GHz. The load-switch provides up to 10% efficiency improvement at 0.9GHz for reduced power level

Ruggedness improvement by protection

Cellular phone power amplifier transistors have to withstand extreme voltages, temperatures and currents. Requirements on IC and packaging technology are relaxed by using over-voltage and over-temperature protection. To avoid breakdown, protection circuits are used that detect the collector peak voltage and die temperature to limit the output power once a threshold level is crossed. For a supply voltage of 5 V and a nominal output power of 2W, no breakdown is observed for a VSWR of 10 over all phases. For a VSWR of 4 and worst case mismatch phase the maximum die temperature is reduced from 143degC to 112degC when the output power is adaptively reduced from 32.1 dBm to 27.7 dB