Weak antilocalization in quasi-two-dimensional electronic states of epitaxial LuSb thin films

Observation of large non-saturating magnetoresistance in rare-earth monopnictides has raised enormous interest in understanding the role of its electronic structure. Here, by a combination of molecular-beam epitaxy, low-temperature transport, angle-resolved photoemssion spectroscopy, and hybrid density functional theory we have unveiled the bandstructure of LuSb, where electron-hole compensation is identified as a mechanism responsible for large magnetoresistance in this topologically trivial compound. In contrast to bulk single crystal analogues, quasi-two-dimensional behavior is observed in our thin films for both electron and holelike carriers, indicative of dimensional confinement of the electronic states. Introduction of defects through growth parameter tuning results in the appearance of quantum interference effects at low temperatures, which has allowed us to identify the dominant inelastic scattering processes and elucidate the role of spin-orbit coupling. Our findings open up new possibilities of band structure engineering and control of transport properties in rare-earth monopnictides via epitaxial synthesis.Comment: 20 pages, 12 figures; includes supplementary informatio

Why Virtue Ethics?

Contemporary virtue ethics, an agent-centred ethical theory, has been presented as a response to inadequacies in more traditional act-centred theories. In this paper, I argue that such a response is insufοcient: contemporary virtue ethics fails to avoid the inadequacies that it purports to avoid, and brings with it problems of its own. This paper is divided into 5 sections, in the οrst of which I introduce contemporary virtue ethics as an agent-centred and pluralistic ethical theory. In section 2, I present inadequacies that virtue ethics claims to avoid: being too reductive, too algorithmic, too abstract, self-effacing, and self-other asymmetric. In section 3, I consider and analyse virtue ethics’ account of right action and of motives in order to argue in section 4 that, if these inadequacies are indeed problems affecting traditional ethical theories, virtue ethics does not avoid these problems either— particularly because of its basis in the concept of virtues and its heavy reliance on phronesis. I show that another ethical theory, limited moral pluralism, has the same advantages of not being overly reductive, algorithmic, or abstract, and being self-other symmetric, and that virtue ethics does not avoid self-effacement as it claims to. I also question here whether self-effacement and self-other asymmetry should be considered problems when evaluating moral theories. Finally, I suggest in section 5 that virtue ethics is open to further criticisms of indeterminacy and lack of explanatory power

Revealing quantum Hall states in epitaxial topological half-Heusler semimetal

Prediction of topological surface states (TSS) in half-Heusler compounds raises exciting possibilities to realize exotic electronic states and novel devices by exploiting their multifunctional nature. However, an important prerequisite is identification of macroscopic physical observables of the TSS, which has been difficult in these semi-metallic systems due to prohibitively large number of bulk carriers. Here, we introduce compensation alloying in epitaxial thin films as an effective route to tune the chemical potential and simultaneously reduce the bulk carrier concentration by more than two orders of magnitude compared to the parent compound. Linear magnetoresistance is shown to appear as a precursor phase that transmutes into a TSS induced quantum Hall phase on further reduction of the coupling between the surface states and the bulk carriers. Our approach paves the way to reveal and manipulate exotic properties of topological phases in Heusler compounds.Comment: 8 pages, 4 figures. Supplementary Infromation contains 7 sections and 17 figure

Development of Scalable Quantum Nano-Electronic Devices Using Bottom-Up and Top-Down Fabrication

The invention of integrated circuits (ICs) in the 1960s and the subsequent microelectronics revolution fundamentally altered every aspect of modern technology, ranging from communication to computation and healthcare. Through the last few decades, continued miniaturization of such ICs has led to rapid improvements of device functionalities as well as exponentially reducing cost, thus making these technologies more accessible to everyone. This aggressive scaling has however, pushed device features towards sub-100 nanometer regimes, challenging conventional fabrication techniques. Semiconductor nanostructures can circumvent these challenges and enable further scaling for advanced logic and memory devices. Additionally, such nanostructures exhibit electronic and optical properties, that are of tremendous interest for alternative computing architectures such as quantum computing and photonic circuits, or to build power efficient and ultrafast platforms through low-energy and spin-based devices. Fabricating such nanostructures is not trivial but can be achieved through both “top-down” and “bottom-up” approaches. Top-down approaches, which are commonly followed in the semiconductor industry typically start with a bulk material and fabricate nanostructures through various etching steps. Although this technique is scalable and has been extremely successful in building modern ICs, the damage induced from etching can prove detrimental to the performance of low-dimensional systems. Bottom-up techniques generally refer to growing the nanostructures in an additive method in pre-defined positions on a wafer. Bottom-up approaches have the inherent advantage of exhibiting less defects, due to the elimination of etching steps and can be combined with in-situ patterning to build novel hybrid devices. However, these techniques are simultaneously more challenging to integrate and scale up reliably. For optimal performance of such nanostructures, it is critical to have precise control over their chemical composition, geometries, and material qualities. In this thesis, we will explore both bottom-up and top-down approaches, to achieve such defect-free scalable nanostructures in the context of low-power electronics and quantum computing. For bottom-up approaches, we investigate two templated epitaxial growth techniques: confined epitaxial lateral overgrowth (CELO) to grow III-V lateral heterostructures and selective area growth (SAG) to grow in-plane III-V nanowires coupled to superconductors. We first discuss the inherent advantages of CELO to fabricate low-power tunneling devices. Next, we explore the use of growth conditions to reduce defects, engineer facets and improve the material qualities and morphologies in CELO nanostructures. Using this, we demonstrate high-quality lateral III-V quantum wells for heterojunction tunnel transistors. For in-plane selective area growths, we investigate the effect of fundamental parameters such as growth temperature, cooldown processes and nanowire orientation and geometries on the nucleation of highly lattice mismatched heterostructures (indium arsenide on indium phosphide). These nanowires can lead to the fabrication of scalable systems with enhanced electrical and optical properties. We also develop in-situ shadowing techniques to create patterned heterostructures of dissimilar materials with pristine disorder-free interfaces. Subsequently, we use this to demonstrate superconductor-semiconductor hybrid nanowire networks for probing low-temperature effects in topologically non-trivial systems. In the last part of this dissertation, we will shift our focus to top-down techniques for defining aluminum/silicon/aluminum trilayer nanostructures with extreme aspect ratios. Such nanostructures can reduce footprint and enable scaling up of Josephson-junction based superconducting qubit systems. In conclusion, using both bottom-up and top-down techniques we combine advanced fabrication and epitaxial growth to achieve defect-free III-V scalable nanostructures with disorder-free interfaces. In the future, these nanostructures will enable the scalable fabrication of next-generation efficient computing platforms