Active inductor shunt peaking in high-speed VCSEL driver design

An all transistor active inductor shunt peaking structure has been used in a prototype of 8-Gbps high-speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS process for radiation tolerant purpose. The all transistor active inductor shunt peaking is used to overcome the bandwidth limitation from the CMOS process. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been tapped out, and the prototype has been proofed by the preliminary electrical test results and bit error ratio test results. The driver achieves 8-Gbps data rate as simulated with the peaking. We present the all transistor active inductor shunt peaking structure, simulation and test results in this paper.Comment: 4 pages, 6 figures and 1 table, Submitted to 'Chinese Physics C

Development of A 16:1 serializer for data transmission at 5 Gbps

Radiation tolerant, high speed and low power serializer ASIC is critical for optical link systems in particle physics experiments. Based on a commercial 0.25 μm silicon-onsapphire CMOS technology, we design a 16:1 serializer with 5 Gbps serial data rate. This ASIC has been submitted for fabrication. The post-layout simulation indicates the deterministic jitter is 54 ps (pk-pk) and random jitter is 3 ps (rms). The power consumption of the serializer is 500 mW. The design details and post layout simulation results are presented in this paper

High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers

We develop a custom Bit Error Rate test bench based on Altera’s Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial stand alone tester. The 8B/10B protocol is implemented and its effects studied. A variable optical attenuator is inserted in the fibre loop to induce transmission degradation and to measure receiver sensitivity. We report comparable receiver sensitivity results using the FPGA based tester and commercial tester. The results of the FPGA also shows that there are more one-tozero bit flips than zero-to-one bit flips at lower error rate. In 8B/10B coded transmission, there are more word errors than bit flips, and the total error rate is less than two times that of non-coded transmission. Total error rate measured complies with simulation results, according to the protocol setup

The Design of a High Speed Low Power Phase Locked Loop

The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25-μm Silicon-on- Sapphire (SoS) CMOS technology. Post-layout simulation indicates that tuning range is 3.79 – 5.01 GHz and power consumption is 104 mW. The PLL has been submitted for fabrication. The design and simulation results are presented

Design and hardware evaluation of the optical-link system for the ATLAS Liquid Argon Calorimeter Phase-II Upgrade

An optical link system is being developed for the ATLAS Liquid Argon Calorimeter Phase-II upgrade. The optical link system is responsible for transmit the data of over 182 thousand detector channels from 1524 Front-End Boards (FEBs) through 26 optical fibers per FEB over 150 meters to the counting room and brings clocks, bunch crossing reset signals and slow control/monitoring signals back to the FEBs. The optical link system is based on the Low-Power GigaBit Transceivers (lpGBTs) and the Versatile optical Transceiver (VTRx+) modules, which both are being developed for the High-Luminosity LHC upgrade. An evaluation board is designed and the major functions of the optical link system are being evaluated. The design of the optical link system and the evaluation of major functions are presented in the paper.Comment: 12 pages, 8 figure

1.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLAS Inner Tracker Pixel Detector Upgrade

We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout upgrade. The first prototype, GBCR1, has four upstream receiver channels and one downstream transmitter channel with pre-emphasis. Each upstream channel receives the data at 5.12 Gbps through a 5 meter AWG34 Twinax cable from an ASIC driver located on the pixel module and restores the signal from the high frequency loss due to the low mass cable. The signal is retimed by a recovered clock before it is sent to the optical transmitter VTRx+. The downstream driver is designed to transmit the 2.56 Gbps signal from lpGBT to the electronics on the pixel module over the same cable. The peak-peak jitter (throughout the paper jitter is always peak-peak unless specified) of the restored signal is 35.4 ps at the output of GBCR1, and 138 ps for the downstream channel at the cable ends. GBCR1 consumes 318 mW and is tested. The second prototype, GBCR2, has seven upstream channels and two downstream channels. Each upstream channel works at 1.28 Gbps to recover the data directly from the RD53B ASIC through a 1 meter custom FLEX cable followed by a 6 meter AWG34 Twinax cable. The equalized signal of each upstream channel is retimed by an input 1.28 GHz phase programmable clock. Compared with the signal at the FLEX input, the additional jitter of the equalized signal is about 80 ps when the retiming logic is o . When the retiming logic is on, the jitter is 50 ps at GBCR2 output, assuming the 1.28 GHz retiming clock is from lpGBT. The downstream is designed to transmit the 160 Mbps signal from lpGBT through the same cable connection to RD53B and the jitter is about 157 ps at the cable ends. GBCR2 consumes about 150 mW when the retiming logic is on. This design was submitted in November 2019.Comment: 7 pages, 15 figure

MUX64, an analogue 64-to-1 multiplexer ASIC for the ATLAS High Granularity Timing Detector

We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 degrees celsius shows negligible degradation over 16 days