Microwave Integrated CMOS Oscillators on Silicon-on-insulator Substrate

This paper shows the feasibility of implementing CMOS microwave oscillators on Silicon-on-Insulator (SOI) substrate at 5.8 and 12 GHz. The oscillators have been designed by introducing in a circuit simulator (SPICE) the SOI MOSFET’s models developed at our laboratory. The models and the fabrication process of 0.25 µm channel length Fully Depleted (FD) SOI MOSFET’s were not yet optimized for the first oscillator designs presented in this paper. However, the results show the potentiality of SOI CMOS technology for building low-power, low-voltage RF circuits

Direct extraction techniques of microwave small-signal model and technological parameters for sub-quarter micron SOI MOSFETs

Original extraction techniques of microwave small-signal model and technological parameters for SOI MOSFETs are presented. The characterization method combines careful design of probing and calibration structures, rigorous in situ calibration and a powerful direct extraction method. The proposed characterization procedure is directly based on the physical meaning of each small-signal behavior of each model parameter versus bias conditions, the high frequency equivalent circuit can be simplified for extraction purposes. Biasing MOSFETs under depletion, strong inversion and saturation conditions, certain technological parameters and microwave small-signal elements can be extracted directly from the measured S-parameters. These new extraction techniques allow us to understand deeply the behavior of the sub-quarter micron SOI MOSFETs in microwave domain and to control their fabrication process

Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs

The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lenghts and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 žm FD SOI n-MOSFETs with a total gate width of 100 žm present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for V(ds) = 0.75 V and P(dc) < 3 mW. A maximum extrapolated oscillation frequency of about 70 GHz has been obtained at V(ds) = 1 V and J(ds) = 100 mA/mm. This new generation of MOSFETs presents very good analogical and digital high speed performances with a low power consumption which make them extremely attractive for high frequency portable applications such as the wireless communications

Microwave integrated CMOS oscillators on silicon-on-insulator substrate

This paper shows the feasibility of implementing CMOS microwave oscillators on Silicon-on-Insulator (SOI) substrate at 5.8 and 12 GHz. The oscillators have been designed by introducing into a circuit simulator (SPICE), the SOI MOSFET models developed at our laboratory. The models and the fabrication process of 0.25 mu m channel length fully depleted SOI MOSFET's were not yet optimized for the first oscillator designs presented in this paper. However, the results show the potential of SOI CMOS technology for building low-power, low-voltage RF circuits.Anglai

Deep-submicrometer DC-to-RF SOI MOSFET macro-model

We present a submicrometer RF fully depleted SOI MOSFET macro-model based on a complete extrinsic small-signal equivalent circuit and an improved CAD model for the intrinsic device. The delay propagation effects in the channel are modeled by splitting the intrinsic transistor into a series of shorter transistors, for each of which a quasistatic device model can be used. Since the intrinsic device model is charge-based, our RF SOI MOSFET model can be used in both small and large-signal analyses. The model has been validated for frequencies up to 40 GHz and effective channel lengths down to 0.16 mum