Starting performance of synchronous motors

Imperial Users onl

Measurement of Leakage from Earthen Manure Structures in Iowa

eakage from a representative sample of 28 earthen manure storage structures and lagoons (selected from 459 built in Iowa between 1 January 1987 and 31 December 1994) was determined using a water–balance approach. Forty–three percent (43%) of tested structures had leakage rates significantly (p \u3c 0.05) lower than the regulatory limit of 1.6 mm/d (1/16 in/d) specified by the State of Iowa at the time the basins were constructed. Leakage from 53% of the structures was too close to the regulatory limit to be categorized as being significantly above or below it. One structure (4%) exhibited leakage significantly greater than the regulatory limit. Regression analysis indicates a slight, but statistically significant, decline in leakage rate with increasing structure age. Structures constructed in glacial till showed significantly lower leakage rates than those constructed in sand and gravel, colluvium, or loess. Comparison of slurry pits and lagoons showed no significant difference in leakage rate

Behavior synthesis for high speed 3D color interpolation using VHDL

The purpose of this thesis is to study the methodology of behavioral synthesis and evaluate its usefulness compared to Register Transfer Level (RTL) synthesis. Custom IC design uses high-powered synthesis tools. Engineers have traditionally used RTL level descriptions of their circuits as input to these synthesis tools. As new Behavioral Synthesis tools are becoming more powerful, the option to describe their circuitry in a higher and more abstract level is becoming a more feasible option. Describing circuitry at a higher level has many advantages. It is easier to make architecture changes and higher level descriptions generally have significantly less lines of code and faster development times. To study behavioral synthesis a tri-linear interpolation algorithm is used. An RTL style and two different behavioral styles are used. Each are compared for area, power consumption, synthesis time, code length and throughput. The design is simulated before and after synthesis to verify the accuracy of the design using VHDL. Behavioral Compiler from Synopsys will be used to synthesize the design from VHDL to the gate level. It was found that behavioral synthesis can produce results nearly as good as an RTL described circuit. The results were generally 20% - 30% worse for this implementation using behavioral synthesis