An ensemble approach to accurately detect somatic mutations using SomaticSeq

SomaticSeq is an accurate somatic mutation detection pipeline implementing a stochastic boosting algorithm to produce highly accurate somatic mutation calls for both single nucleotide variants and small insertions and deletions. The workflow currently incorporates five state-of-the-art somatic mutation callers, and extracts over 70 individual genomic and sequencing features for each candidate site. A training set is provided to an adaptively boosted decision tree learner to create a classifier for predicting mutation statuses. We validate our results with both synthetic and real data. We report that SomaticSeq is able to achieve better overall accuracy than any individual tool incorporated. ELECTRONIC SUPPLEMENTARY MATERIAL: The online version of this article (doi:10.1186/s13059-015-0758-2) contains supplementary material, which is available to authorized users

Ramp blue: a message-passing manycore system in FPGAs

We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and was designed to emulate a distributed-memory message-passing architecture. The system consists of 768– 1008 MicroBlaze cores in 64–84 Virtex-II Pro 70 FPGAs on 16–21 BEE2 boards, surpassing the milestone of 1000 cores in a standard 42U rack. An architecture based on point-to-point channels and switches using a combination of custom and generic hardware provides the functionality. Virtual-cut-through dimensional routing on one of two hybrid topologies with virtual channels provides the connectivity. A control network with a tree topology provides management and debugging capabilities. A software infrastructure consisting of GCC, uClinux and UPC allows running off-the-shelf applications and scientific benchmarks. Initial performance is encouraging for emulation purposes. In this paper we report on the design and implementation of RAMP Blue and discuss our experiences and lessons learned. and provide insight into the problems with and limits of FPGA emulation of massively parallel multi-core architectures [2]. In this paper we summarize the design and implementation of RAMP Blue and document some critical BEE2 infrastructure shared by RAMP Blue and other applications. Section 2 documents the gateware 1 and software infrastructure developed for the BEE2. Section 3 describes the design and architecture of RAMP Blue. Section 4 describes the implementation and status of RAMP Blue. Section 5 concludes and discusses future work. 2. BERKELEY EMULATION ENGINE 2 The BEE2 is a second-generation FPGA board developed at the Berkeley Wireless Research Center (BWRC) and was designed for a broad range of applications, including realtime DSP, scientific computing and high-performance reconfigurable computing [3]. This broad domain is reflected in the BEE2’s architecture, shown in Figure 1

Additional file 1 of An ensemble approach to accurately detect somatic mutations using SomaticSeq

Supplementary text. It contains detailed results of our analyses in Figures S1–S7 and Tables S1–S19. It also describes the location of the data used in this paper. (PDF 531 kb