7 research outputs found

    High mobility and quantum well transistors: design and TCAD simulation

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    For many decades, the semiconductor industry has miniaturized transistors, delivering increased computing power to consumers at decreased cost. However, mere transistor downsizing does no longer provide the same improvements. One interesting option to further improve transistor characteristics is to use high mobility materials such as germanium and III-V materials. However, transistors have to be redesigned in order to fully benefit from these alternative materials. High Mobility and Quantum Well Transistors: Design and TCAD Simulation investigates planar bulk Germanium pFET technology in chapters 2-4, focusing on both the fabrication of such a technology and on the process and electrical TCAD simulation. Furthermore, this book shows that Quantum Well based transistors can leverage the benefits of these alternative materials, since they confine the charge carriers to the high-mobility material using a heterostructure. The design and fabrication of one particular transistor structure - the SiGe Implant-Free Quantum Well pFET – is discussed. Electrical testing shows remarkable short-channel performance and prototypes are found to be competitive with a state-of-the-art planar strained-silicon technology. High mobility channels, providing high drive current, and heterostructure confinement, providing good short-channel control, make a promising combination for future technology nodes

    High Mobility and Quantum Well Transistors

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    Numerical analysis of the new implant-free quantum-well CMOS: DualLogic approach

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    The research into alternative channel materials to improve CMOS performance is a rapidly growing area of research. III–V and Ge based MOSFETs offer attractive possibilities for a high performance and low power circuit implementation. Here, we report a global performance analysis of future DualLogic CMOS based on the new, Implant-FreeQuantum-Well device architecture for both III–V nMOSFETs and Ge pMOSFETs. The III–V nMOSFETs are optimised to achieve low leakage, high performance and its performance is evaluated using ensemble Monte Carlo simulations. A similar approach is adopted for the Ge pMOSFETs. In addition, the impact of the interface states density on the output characteristics is also studied. Finally, the timing performance of the DualLogic CMOS is evaluated using mixed mode TCAD and circuit simulations

    Silicon and selenium implantation and activation in In0.53Ga0.47As under low thermal budget conditions

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    Si and Se implantations have been systematically investigated in In0.53Ga0.47As. Different implant doses and various activation anneals with temperatures up to 700 degrees C have been examined. Raising Si implant dose from 1 x 10(14) to 1 x 10(15) cm(-2) was found to increase the active doping concentration by about a factor of two. As confirmed by Transmission Electron Microscopy (TEM) and electrical measurements, the rest of the implanted Si ions remain as defects in the crystal and degrade the mobility. It was also confirmed from Secondary Ion Mass Spectrometry (SIMS) that the Si diffusivity in InGaAs is negligible up to 700 degrees C implant activation anneal making Si a suitable option for the formation of shallow junctions in InGaAs. The activation efficiency, sheet resistance, carrier density and mobility data of 25 keV Se and Si implanted InGaAs layers are also presented under various activation anneal temperatures. (C) 2010 Elsevier B.V. All rights reserved.status: publishe

    The implant-free quantum well field-effect transistor: Harnessing the power of heterostructures

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    The Implant-Free Quantum Well Field-Effect Transistor (FET) offers enhanced scalability in a planar architecture through the integration of heterostructures. The Implant-Free architecture fully utilizes the band offsets between different materials, whereby charge carriers are effectively confined to a thin channel layer. This prevents sub-surface source/drain leakage observed in classical bulk Metal-Oxide-Semiconductor FETs at small gate lengths. An investigation of the V-T-tuning capabilities of this technology reveals sensitivity to both well doping and bulk voltage. (C) 2011 Elsevier B. V. All rights reserved.status: publishe
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