Testing of modern semiconductor memory structures

In this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application requirements. The embedded memories are expected to utilize more than 60% of the chip area after 2009. In addition, future SoCs are believed to embed memories of increasing capacities. As a result, the overall SoC yield will be dominated by the memory yield. This trend may make the overall yield unacceptable, unless special measures have been taken. In this thesis we propose and classify DRAM specific fault models relevant for the state-of-the-art semiconductor technologies. We also define and validate a set of DRAM targeted march tests. In addition, we propose a methodology for deriving conditions and tests for linked memory faults. We also investigate the detection conditions for linked memory faults when one of the faults involved is an address decoder fault. Finally, we propose various optimizations for test time reduction and/or increased fault coverage. We aimed at high relevancy of the ideas proposed in this thesis. For as far as possible the fault models and the tests presented here are validated using real industrial products. Some of the concepts originally proposed by the author more than 10 years ago are still being widely used by the industry and referred to by the academia. For example, many industrial products did use or are still using March LR, one of the tests derived in this thesis, for testing their (embedded) memories.Electrical Engineering, Mathematics and Computer Scienc

Real-time FPGA-implementation for blue-sky Detection

Currently, television sets with flat plasma and LCD screens with improved resolutions and better color quality are emerging. To fully utilize their capabilities, lower resolution standard definition video material is enhanced. During such process, existing noise can become clearly visible, or additional artifacts may be introduced. These impairments are usually better visible in smooth image areas such as sky regions, motivating the development of special techniques for their removal. In this paper, we introduce a hardware accelerator for an existing pixel-accurate and spatially-consistent sky-detection algorithm. We describe the algorithmic and architectural design considerations of a resource-efficient real-time system, targeting an FPGA platform. Our results show that it is feasible to implement a simplified algorithm version by using only 5,756 logic-and 23,687 memory elements of the targeted device. A demonstrator setup using real-time camera signal, proves that images of up to 640times480 at a frame rate of 30 fps can be processed. Furthermore, according to our estimations, images with pixel rates up to 142 MHz, e.g. high definition TV, can be processed by the proposed system

Real-time FPGA-implementation for blue-sky Detection

Currently, television sets with flat plasma and LCD screens with improved resolutions and better color quality are emerging. To fully utilize their capabilities, lower resolution standard definition video material is enhanced. During such process, existing noise can become clearly visible, or additional artifacts may be introduced. These impairments are usually better visible in smooth image areas such as sky regions, motivating the development of special techniques for their removal. In this paper, we introduce a hardware accelerator for an existing pixel-accurate and spatially-consistent sky-detection algorithm. We describe the algorithmic and architectural design considerations of a resource-efficient real-time system, targeting an FPGA platform. Our results show that it is feasible to implement a simplified algorithm version by using only 5,756 logic-and 23,687 memory elements of the targeted device. A demonstrator setup using real-time camera signal, proves that images of up to 640times480 at a frame rate of 30 fps can be processed. Furthermore, according to our estimations, images with pixel rates up to 142 MHz, e.g. high definition TV, can be processed by the proposed system

Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power implications, but gives rise to a well-differentiated point in the architecture design space. This in an effect of the tight interaction existing between architecture and physical design layers in nanoscale technologies. This work assesses several NoC link inference techniques (buffering options, link pipelining) by means of commercial backend synthesis tools, taking the system-level perspective. In fact, performance speed-ups and power overhead are not evaluated for the links in isolation but for the network topology as a whole, thus showing their sensitivity to the link inference strategy. k-ary n-mesh topologies are considered for the sake of analysis, in that they provide a range of topologies with increasing total wirelength

Implementation of a reliable date bus for the Delfi nanosatellite programme

The Delfi-n3Xt nano-satellite is the second Dutch universitysatellite currently being developed at the Delft University of Technology (TUD) as successor of the Delfi-C3 that has been successfully launched in April 2008. Compared to Delfi-C3, the Delfi-n3Xt platform provides significant advancements to the platform: a high-speed downlink, three-axis attitude control and a single-point of failure free battery. In total five payloads will be flown that generate a considerable larger amount of data compared to Delfi-C3that implies, as well, a robust and adequate design for the data handling system that interlinks the various embedded systems on board. This paper examines the design and implementation of a fault tolerant data bus architecture as part of the satellite Command and DataHandling Subsystem (CDHS). Delfi-C3 carries an I2C protocol based implementation that currently experiencesproblems with data corruption and timeouts and is therefore subject of scrutiny andanalysis in this paper. In particular, the relationship between error rates, master-slave speeds and processing overheads is evaluated in detail. After a tradeoff study betweenseveral bus standards for Delfi-n3Xt, the choice is once again an I2Cimplementation, but with significant hardware and software improvements over the previous design. In terms of hardware, shielding and bus protection considerationsare included in the very early stages of design. With respect to software, special care is taken in dealing with the varying clock speeds between slaves and masters, correct data handling and the feasibility of error detection and correction codes, as the amount of data generated by thepayloads of the Delfi-n3Xt is significantly higher. The final result of this research is the selection of the most adequate reliability techniques and their implementation. This I2Cbus targeted middleware is intended for usage in the complete Delfi nanosatelliteprogramme at TUD and for several other space applications in general.Space EngineeringAerospace Engineerin

Comparing tightly and loosely couplet mesochronous synchronizers in a NoC switch architecture

With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distribution. Recently proposed schemes agree on a source synchronous design style with some form of ping-pong buffering to counter timing and metastability concerns. However, the integration issues of such synchronizers in a NoC setting are still largely uncovered. Most schemes are in fact placed between communicating switches, thus neglecting the abrupt increase of buffering resources needed at switch input stages. This paper goes a step forward and aims at deep integration of the synchronizer in the switch architecture, thus merging key tasks such as synchronization, buffering and flow control into a unique architecture block. This paper compares the integrated and the loosely coupled solutions from a performance and area viewpoint, while devoting special attention to their robustness with respect to physical design parameters

An attitude determination system suitable for a spacecraft

Delft University of Technolog

A Platform for RFID Security and Privacy Administration

This paper presents the design, implementation, and evaluation of the RFID Guardian, the first-ever unified platform for RFID security and privacy administration. The RFID Guardian resembles an ``RFID firewall,'' that monitors and controls access to RFID tags by combining a standard-issue RFID reader with unique RFID tag emulation capabilities. Our system provides a platform for both automated and coordinated usage of RFID security mechanisms, offering fine-grained control over RFID-based auditing, key management, access control, and authentication capabilities. We have prototyped the RFID Guardian using off-the-shelf components, and our experience has shown that active mobile devices are a valuable tool for managing the security of RFID tags in a variety of applications, including protecting low-cost tags that are unable to regulate their own usage. More philosophically, RFID technology vividly illustrates the difficulties of security administration in a world of increasingly pervasive, decentralized, low-cost, and low-power computing. Our paper thus also offers a glimpse of what system administration may be like in the future, when laymen face the responsibility to manage systems of tiny computers that they are barely aware of

Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism

Test data travels through a System-on-Chip (SOC) from the chip pins to the module-under-test and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented with dedicated wires. However, also existing functional interconnect, such as a bus or Network-on-Chip (NOC), can be reused as TAM. This will reduce the overall design effort and the silicon area. For a given module, its test set, and maximal bandwidth that the functional interconnect can offer between ATE and module-under-test, our approach designs a test wrapper for the module-under-test such that the test length is minimized. Unfortunately, it is unavoidable that with the test data also unused (idle) bits are transported. This paper presents a TAM bandwidth utilization analysis and techniques for idle bits reduction, to minimize the test length. We classify the idle bits into four types which explain the reason for bandwidth under-utilization and pinpoint design improvement opportunities. Experimental results show an average bandwidth utilization of 80%, while the remaining 20% is consumed by the idle bits. © 2008 IEEE

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them allows fast design time, ease of routing, predictability of electrical parameters and good scalability. k-ary n-mesh topologies are candidate solutions for these systems, borrowed from the domain of off-chip interconnection networks. However, the on-chip integration has to deal with unique challenges at different levels of abstraction. From a technology viewpoint, interconnect reverse scaling causes critical paths to go across global links. Poor interconnect performance might also impact IP core speed depending on the synchronization mechanism at the interface. Finally, this might also conflict with the requirements that communication libraries employed in the MPSoC domain pose on the underlying interconnect fabric. This paper provides a comprehensive overview of these topics, by characterizing physical feasibility of representative k-ary n-mesh topologies and by providing silicon-aware system-level performance figures