Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST

During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, we propose two approaches to reduce the PD generated at capture during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Shift scheme. Both approaches increase the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, the AF of the scan chains at capture is reduced. Consequently, the AF of the CUT at capture, thus the PD at capture, is also reduced compared to conventional scan-based LBIST. The former approach, hereinafter referred to as Low-Cost Approach (LCA), enables a 50% reduction in the worst case magnitude of PD during conventional logic BIST. It requires a small cost in terms of area overhead (of approximately 1.5% on average), and it does not increase the number of test vectors over the conventional scan-based LBIST to achieve the same Fault Coverage (FC). Moreover, compared to three recent alternative solutions, LCA features a comparable AF in the scan chains at capture, while requiring lower test time and area overhead. The second approach, hereinafter referred to as High-Reduction Approach (HRA), enables scalable PD reductions at capture of up to 87%, with limited additional costs in terms of area overhead and number of required test vectors for a given target FC, over our LCA approach. Particularly, compared to two of the three recent alternative solutions mentioned above, HRA enables a significantly lower AF in the scan chains during the application of test vectors, while requiring either a comparable area overhead or a significantly lower test time. Compared to the remaining alternative solutions mentioned above, HRA enables a similar AF in the scan chains at capture (approximately 90% lower than conventional scan-based LBIST), while requiring a significantly lower test time (approximately 4.87 times on average lower number of test vectors) and comparable area overhead (of approximately 1.9% on average)

Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems

THE continuous scaling of microelectronic technology, while allowing to integrate increasingly complex and high performance systems on a die, poses new challenges to their reliable operation in the field, due to the increased likelihood of faults and aging phenomena possibly occurring in the field and compromising the system\u2019s correct operation. Several on-line testing and error/fault resilience techniques have been employed in the past to implement highly reliable, fault tolerant systems for mission critical applications, in areas like space, military, automotive, medical, banking, etc. However, new faults and aging phenomena occurring in the field are posing unique on-line testing and error/fault resilience challenges even for mainstream applications, where cost is a crucial factor. This mandates the development and adoption of innovative solutions optimized for cost, power and area

Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems

This Special Section consists of eleven articles that have been selected to provide the readers with a single comprehensive reference of theoretical and practical aspects of innovative techniques for on-line testing and error/fault resilience of electronic systems, possibly adopted to face the challenges in reliability of today's complex electronic systems, including high performance microprocessors, multi-core systems, real time systems and systems for cryptographic applications

Function-inherent code checking: A new low cost on-line testing approach for high performance microprocessor control logic

We propose an on-line testing approach for the control logic of high performance microprocessors. Rather than adding information redundancy (in the form of error detecting codes), we propose to look for the information redundancy (referred to as Function-Inherent Codes) that the microprocessor control logic may inherently have, due to its required functionality. We will show that this allows to achieve on-line testing at significant savings in terms of area and power consumption, and with lower or comparable impact on system performance and design costs, compared to alternate, traditional on-line testing approaches. © 2008 IEEE

Function Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic

We propose a new on-line testing approach for the control logic of high performance microprocessors. Rather than adding information redundancy (in the form of traditional error detecting codes), we propose to look for the information redundancy (referred to as Hidden Codes) that the microprocessor control logic may already inherently have, due to its required functionality. We will show that this allows to achieve on-line testing at significant savings in terms of area and power consumption, and with lower or comparable impact on system performance and design costs, compared to alternate, traditional on-line testing approaches

Low cost concurrent error detection strategy for the control logic of high performance microprocessors and its application to the instruction decoder

We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, Serviceability (RAS) of high performance microprocessors, by specifically targeting one of its most critical blocks (from the point of view of the microprocessor RAS), that is the control logic. By discovering codes that are inherently present within the control logic because of its performed functionality and verification needs (referred to as Control Logic Function-Inherent Codes), it allows to achieve concurrent error detection at very limited costs in terms of area, power consumption, impact on performance and design. Considering for instance the case of the instruction decoder of a public domain microprocessor, we will prove that our approach requires significantly lower area and power than traditional parity encoding, while providing higher concurrent error detection ability. Therefore, if adopted together with a system level (generally software implemented) recovery technique, our strategy constitutes a viable and successful approach to increase the microprocessor RAS, at very limited costs. © 2013 Springer Science+Business Media New York

Power droop reduction during Launch-On-Shift scan-based logic BIST

The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a concern for modern ICs. In fact, during test, PD may significantly increase the delay of signals of the circuit under test (CUT), an effect that may be erroneously recognized as presence of delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel approach to reduce PD during at-speed test with scan-based Logic BIST using the Launch-On-Shift scheme. Our approach increases the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, when the test vectors are applied, the activity factor (AF) of the scan chains is reduced by approximately the 50% with respect to conventional scan-based LBIST, with no drawbacks on test length and fault coverage, and at the cost of very limited area overhead. We also show that compared to two recent alternate solutions, our approach features a comparable AF in the scan chains during the application of test vectors, while it requires a significantly lower test time or area overhead