Structural and Electrical Properties of HfO2/n-InxGa1-xAs structures (x: 0, 0.15, 0.3 and 0.53)

7th International Symposium on High Dielectric Constant Materials and Gate Stacks - 216th Meeting of the Electrochemical Society; Vienna; Austria; 5 October 2009 through 7 October 2009; Code 79118In this work results are presented of an investigation into the structural and electrical properties of HfO2 films on GaAs and InxGa1-xAs substrates for x: 0.15, 0.30, and 0.53. The capacitancevoltage responses of the GaAs and InxGa1-xAs (x: 0.15 and 0.30) are dominated by an interface defect response. Analysis of these samples at 77K indicates that the defect density is > 2.5x1013 cm-2. For the HfO2/In0.53Ga0.47As system, 77K capacitance-voltage responses indicate surface accumulation is achieved. The results are consistent with a high defect density, with an energy level {greater than or equal to}0.75 eV above the valence band in the HfO2/InxGa1-xAs system, where the defect energy with respect to the valence band, does not change with the composition of the InxGa1-xAs. The HfO2/In0.53Ga0.47As interface exhibits two defects at 0.3eV (1.7x1013cm-2eV) and 0.61eV (1.5x1013cm-2eV) above the valance band edge. The defect at 0.61eV is removed by forming gas annealing at 325oC

Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1-x and InxGa1-xAs: Part I-Model Description and Validation

High-mobility alternative channel materials to silicon are critical to the continued scaling of MOS devices. The analysis of capacitance-voltage (C-V) measurements on these new materials with high-k gate dielectrics is a critical technique to determine many important gate-stack parameters. While there are very useful C-V analysis tools available to the community, these tools are all limited in their applicability to alternative semiconductor channel MOS gate-stack analysis since they were developed for silicon. Here, we report on a new comprehensive C-V simulation and extraction tool, called CV Alternative Channel Extraction (ACE), that incorporates a wide range of semiconductors and dielectrics with the capability to implement customized gate stacks. Fermi-Dirac carrier statistics, nonparabolic bands, and quantum mechanical effects are all implemented with options to turn each of these off as the user desires. Interface state capacitance (Cit) is implemented using a common model for systems like Si and Ge. A more complex Cit model is also implemented for III-Vs that accurately captures frequency dispersion in accumulation that arises from tunneling. CV ACE enables extremely fast simulation and extraction and can accommodate measurements performed at variable temperatures and frequencies to allow for a more accurate extraction of interface state density (Dit)

Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1-x and InxGa1-xAs: Part II-Fits and Extraction from Experimental Data

Capacitance-voltage (C-V) measurement and analysis is highly useful for determining important information about MOS gate stacks. Parameters such as the equivalent oxide thickness (EOT), substrate doping density, flatband voltage, fixed oxide charge, density of interface traps (Dit), and effective gate work function can all be extracted from experimental C-V curves. However, to extract these gate-stack parameters accurately, the correct models must be utilized. In Part I, we described the modeling and implementation of a C-V code that can be used for alternative channel semiconductors in conjunction with high-k gate dielectrics and metal gates. Importantly, this new code (CV ACE) includes the effects of nonparabolic bands and quantum capacitance, enabling accurate models to be applied to experimental C-V curves. In this paper, we demonstrate the capabilities of this new code to extract accurate parameters, including EOT and Dit profiles from experimental high-k on Ge and In0.53Ga0.47As gate stacks