The Modern FPGA as Discriminator, TDC and ADC

Recent generations of Field Programmable Gate Arrays (FPGAs) have become indispensible tools for complex state machine control and signal processing, and now routinely incorporate CPU cores to allow execution of user software code. At the same time, their exceptional performance permits low-power implementation of functionality previously the exclusive domain of dedicated analog electronics. Specific examples presented here use FPGAs as discriminator, time-to-digital (TDC) and analog-to-digital converter (ADC). All three cases are examples of instrumentation for current or future astroparticle experiments.Comment: 7 pages, v3 minor JINST editorial correction

A Monolithic Time Stretcher for Precision Time Recording

Identifying light mesons which contain only up/down quarks (pions) from those containing a strange quark (kaons) over the typical meter length scales of a particle physics detector requires instrumentation capable of measuring flight times with a resolution on the order of 20ps. In the last few years a large number of inexpensive, multi-channel Time-to-Digital Converter (TDC) chips have become available. These devices typically have timing resolution performance in the hundreds of ps regime. A technique is presented that is a monolithic version of ``time stretcher'' solution adopted for the Belle Time-Of-Flight system to address this gap between resolution need and intrinsic multi-hit TDC performance.Comment: 9 pages, 15 figures, minor corrections made, to appear as JINST_008

The first version Buffered Large Analog Bandwidth (BLAB1) ASIC for high luminosity collider and extensive radio neutrino detectors

Future detectors for high luminosity particle identification and ultra high energy neutrino observation would benefit from a digitizer capable of recording sensor elements with high analog bandwidth and large record depth, in a cost-effective, compact and low-power way. A first version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRADOR ASIC has been very successful and forms the basis of a generation of new, large-scale radio neutrino detectors, its limited sampling depth is a major drawback. A prototype has been designed and fabricated with 65k deep sampling at multi-GSa/s operation. We present test results and directions for future evolution of this sampling technique.Comment: 15 pages, 26 figures; revised, accepted for publication in NIM

High Voltage CMOS Control Interface for Astronomy - Grade Charged Coupled Devices

The Pan-STARRS telescope consists of an array of smaller mirrors viewed by a Gigapixel arrays of CCDs. These focal planes employ Orthogonal Transfer CCDs (OTCCDs) to allow on-chip image stabilization. Each OTCCD has advanced logic features that are controlled externally. A CMOS Interface Device for High Voltage has been developed to provide the appropiate voltage signal levels from a readout and control system designated STARGRASP. OTCCD chip output levels range from -3.3V to 16.7V, with two different output drive strenghts required depending on load capacitance (50pF and 1000pF), with 24mA of drive and a rise time on the order of 100ns. Additional testing ADC structures have been included in this chip to evaluate future functional additions for a next version of the chip.Comment: 13 pages, 17 gigure

The PRO1 ASIC for Fast Wilkinson Encoding

Wilkinson conversion of stored samples in large Switch Capacitor Array (SCA) ASICs, such as used for high speed waveform sampling, has many benefits in terms of compactness, no missing output codes, low power requirements and robustness. However such Analog-to-Digital conversions are relatively slow, limited by the encoder clock speed. By repeating the same fast sampling technique used by the SCA, combined with a fast priority encoder, significantly faster conversion is demonstrated for a prototype ASIC designated PRO1. For 8-10 bits of resolution, this technique is compact and requires far fewer system resources.Comment: 10 pages, 11 figure

ARGG-HDL: A High Level Python Based Object-Oriented HDL Framework

We present a High-Level Python-based Hardware Description Language (ARGG-HDL), It uses Python as its source language and converts it to standard VHDL. Compared to other approaches of building converters from a high-level programming language into a hardware description language, this new approach aims to maintain an object-oriented paradigm throughout the entire process. Instead of removing all the high-level features from Python to make it into an HDL, this approach goes the opposite way. It tries to show how certain features from a high-level language can be implemented in an HDL, providing the corresponding benefits of high-level programming for the user