Fermion Chern Simons Theory of Hierarchical Fractional Quantum Hall States

We present an effective Chern-Simons theory for the bulk fully polarized fractional quantum Hall (FQH) hierarchical states constructed as daughters of general states of the Jain series, {\it i. e.} as FQH states of the quasi-particles or quasi-holes of Jain states. We discuss the stability of these new states and present two reasonable stability criteria. We discuss the theory of their edge states which follows naturally from this bulk theory. We construct the operators that create elementary excitations, and discuss the scaling behavior of the tunneling conductance in different situations. Under the assumption that the edge states of these fully polarized hierarchical states are unreconstructed and unresolved, we find that the differential conductance $G$ for tunneling of electrons from a Fermi liquid into {\em any} hierarchical Jain FQH states has the scaling behavior $G\sim V^\alpha$ with the universal exponent $\alpha=1/\nu$, where $\nu$ is the filling fraction of the hierarchical state. Finally, we explore alternative ways of constructing FQH states with the same filling fractions as partially polarized states, and conclude that this is not possible within our approach.Comment: 10 pages, 50 references, no figures; formerly known as "Composite Fermions: The Next Generation(s)" (title changed by the PRB thought police). This version has more references and a discussion of the stability of the new states. Published version. One erroneous reference is correcte

Low-Power, High-Throughput, Unsigned Multiplier Using a Modified CPL Adder Cell for Signal Processing Circuit

This paper proposes a full adder circuit that was designed by the Multiplexing Control Input Technique (MCIT) for a sum operation and the Boolean identities used for the carry operation. The proposed adder was implemented into the design of an 8x8-bit array multiplier circuit, specifically Braun, Baugh-Wooley (a 2’s complement generator) and Modified Baugh-Wooley (with optimised interconnections) circuits that were designed for unsigned numbers. The 8x8-bit multiplier circuit was schematised by the DSCH2 VLSI CAD tool, whereas their layouts were generated by the Microwind 3 VLSI CAD tool. Output parameters, such as propagation delay, total chip area, and power dissipation are calculated from the simulated results. This paper extends to analyses for Energy Per Instruction (EPI), throughput, and latency by using the BSIM 4 advanced analyser. The power dissipation, EPI, throughput and area were analysed for different feature size. From these analyses of simulated results, it was found that the proposed adder-based multiplier circuit achieves better power dissipation and throughput performance than existing circuits

A comprehensive analytical study of electrical properties of carbon nanotube field-effect transistor for future nanotechnology

This paper discusses a comprehensive analytical study of electrical properties of single‐wall conventional carbon nanotube field‐effect transistor (CNTFET) devices of subthreshold swing (SS), transconductance (gm), and extension resistance. The analytical expressions for SS and gm have been derived based on channel modulated potential. In the study, it was observed that SS value of the CNTFET device is equal to 60 mV/decade, which is smaller than the conventional and double gate metal‐ oxide‐semiconductor field‐effect transistors. The subthreshold swing degrades at larger tube's diameter and gate‐source voltage due to increased source‐drain leakage current. Carbon nanotube field‐effect transistor devices achieve larger gm at large gate‐source voltage, which has a disadvantage of reducing the allowable voltage swing at the drain. The extension resistance of the device falls with diameter of the tube