Low-Power, High-Throughput, Unsigned Multiplier Using a Modified CPL Adder Cell for Signal Processing Circuit

Abstract

This paper proposes a full adder circuit that was designed by the Multiplexing Control Input Technique (MCIT) for a sum operation and the Boolean identities used for the carry operation. The proposed adder was implemented into the design of an 8x8-bit array multiplier circuit, specifically Braun, Baugh-Wooley (a 2’s complement generator) and Modified Baugh-Wooley (with optimised interconnections) circuits that were designed for unsigned numbers. The 8x8-bit multiplier circuit was schematised by the DSCH2 VLSI CAD tool, whereas their layouts were generated by the Microwind 3 VLSI CAD tool. Output parameters, such as propagation delay, total chip area, and power dissipation are calculated from the simulated results. This paper extends to analyses for Energy Per Instruction (EPI), throughput, and latency by using the BSIM 4 advanced analyser. The power dissipation, EPI, throughput and area were analysed for different feature size. From these analyses of simulated results, it was found that the proposed adder-based multiplier circuit achieves better power dissipation and throughput performance than existing circuits