The Superconducting TESLA Cavities

The conceptional design of the proposed linear electron-positron collider TESLA is based on 9-cell 1.3 GHz superconducting niobium cavities with an accelerating gradient of Eacc >= 25 MV/m at a quality factor Q0 > 5E+9. The design goal for the cavities of the TESLA Test Facility (TTF) linac was set to the more moderate value of Eacc >= 15 MV/m. In a first series of 27 industrially produced TTF cavities the average gradient at Q0 = 5E+9 was measured to be 20.1 +- 6.2 MV/m, excluding a few cavities suffering from serious fabrication or material defects. In the second production of 24 TTF cavities additional quality control measures were introduced, in particular an eddy-current scan to eliminate niobium sheets with foreign material inclusions and stringent prescriptions for carrying out the electron-beam welds. The average gradient of these cavities at Q0 = 5E+9 amounts to 25.0 +- 3.2 MV/m with the exception of one cavity suffering from a weld defect. Hence only a moderate improvement in production and preparation techniques will be needed to meet the ambitious TESLA goal with an adequate safety margin. In this paper we present a detailed description of the design, fabrication and preparation of the TESLA Test Facility cavities and their associated components and report on cavity performance in test cryostats and with electron beam in the TTF linac. The ongoing R&D towards higher gradients is briefly addressed.Comment: 45 pages (Latex), 39 figures (Encapsulated Postscript), 53 Author

Design of Self-Dual Fault-Secure Combinational Circuits

The method of alternating inputs is an interesting combination of time- and hardware-redundancy for error detection of self-dual circuits. In this paper it is shown how a combinational self-dual circuit can be transformed into a self-dual fault-secure circuit. For 82% of the benchmark circuits the necessary average area overhead is only 8,81%. A selfdual circuit is called self-dual fault-secure it every error due to a single stuck-at fault is immediately detected. Faults are detected if, for alternating inputs, the outputs of the faulty circuit are not alternating

Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits

A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs of the circuit is selected to realize a simple characteristic function such that CED is disabled whenever the inputs belong to the OFF-set of the characteristic function. This don't-care space in the operation of the CED circuitry is used to optimize the CED circuitry during synthesis. It is shown that this methodology is very effective at targeting faults with a high sensitization probability. Experimental results show that the proposed approach, which is of special interest in applications where a low-cost CED solution is desired, achieves a significant reduction in the error rate in logic circuits