Symbolic analysis tools-the state of the art

This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state of the art in this field is also studied, pointing out directions for future research

Adaptació curricular de la unitat didàctica “La representació dels objecte” a l'aula de tecnologia, per alumnes nouvinguts

La present memòria recull una proposta d’adaptació curricular de la unitat didàctica “La representació dels objectes”, per a la matèria de Tecnologia de 1r Curs d’ESO. Aquesta adaptació curricular és pensada per a dos grans grups d’alumnes, diferenciats per l’origen de la seva llengua materna. Així, en el cas dels alumnes nouvinguts que tenen com a llengua materna una parla d’origen romànic, l’adaptació curricular es trobarà basada en proporcionar l’origen etimològic de les paraules clau de cada lliçó, facilitant el procés d’aprenentatge donada la similitud dels mots amb els de la seva llengua. En canvi, pels alumnes que tenen com a llengua materna una parla d’origen no romànic, l’adaptació curricular es basarà en fer la matèria més visual, és a dir, en proporcionar representacions gràfiques dels termes clau de cada lliçó. A més, el treball també inclou les eines necessàries per a poder conèixer quina és la situació personal i acadèmica de cada alumne nouvingut que arriba al centre, de manera que l’equip docent podrà proporcionar la millor atenció en cada cas. També es proporcionen un seguit d’activitats que serveixen com a suport de les lliçons teòriques, com ara activitats tipus JClic, i també es proposa un cas d’Aprenentatge Basat en Problemes (ABP), molt útil per afavorir la integració dels nous alumnes en l’entorn de l’aula i ensenyar-los, tant a ells com a la resta d’alumnes, la importància del treball en equip. Al final del treball també es recullen un conjunt de recomanacions que poden facilitar el procés d’integració de l’alumnat, un exemple en seria la proposta d’apadrinatge. Aquesta proposta es basa en assignar a cada alumne nouvingut un “padrí”, que és un alumne que ja era al centre i que ajudarà el nouvingut en el seu procés d’adaptació. Així, per mitjà d’aquest treball s’intenta millorar la integració de l’alumnat nouvingut a l’aula de Tecnologia de 1r d’ESO, facilitant el coneixement de la llengua catalana com a element de cohesió social, ajudant-lo a comprendre la matèria per mitjà de l’adaptació curricular i afavorint la integració en l’entorn del grup-classe amb activitats com l’ABP

MEMS enabled Fabry-Perot cavity for cQED experiments

The development of novel experimental techniques in atomic physics is allowing for the manipulation and control of atoms in structured silicon chips. These new techniques to manipulate atoms in a chip require building micro systems on chip that support actuation, alignment control and tunability for each micro component, which requires a significant integration effort. One example of a new experimental technique in atomic physics is the realization of optical cavities which is a very attractive model for quantum information and communication, because it permits the study of light-matter effect. The important exigency of an integrated micro cavity consisting of a micro mirror and a fiber optics cable are; alignment between them to form a small cavity volume and actuation to allow for adjusment of the cavity length. In this Master thesis the fabrication of 1-D v-shape or chevron thermal actuator is proposed based on the following characteristics: the actuator exploits the thermal expansion property of silicon to generate mechanical actuation, offers linear in-plane displacement, large force in small area compared to other actuators schemes and a shuttle that is capable of carrying an optical fiber that creates an optical cavity between it and a micro-mirror. Additionally, fabrication and characterization techniques are also described for the highly reflective (99.9988\\%) micro-mirrors

Comparison of matroid intersection algorithms for large circuit analysis

This paper presents two approaches to symbolic analysis of large analog integrated circuits via simplification during the generation of the symbolic expressions. Both techniques are examined from the point of view of matroid theory. Finally, a new approach which combines the positive features of both approaches is introduced

Matrix Methods for the Dynamic Range Optimization of Continuous-TimeGm-CFilters

This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differential G m - C filters. Such procedure builds up on a general extended state-space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. Using these methods, an analytical technique for the dynamic range optimization of weakly nonlinear G m - C filters under power dissipation constraints is presented. The procedure is first explained for general filter structures and then illustrated with a simple biquadratic section

A Reuse-based framework for the design of analog and mixed-signal ICs

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.Ministerio de Educación y Ciencia TEC2004-0175

Mismatch distance term compensation in centroid configurations with nonzero-area devices

This paper presents an analytical approach to distance term compensation in mismatch models of integrated devices. Firstly, the conditions that minimize parameter mismatch are examined under the assumption of zero-area devices. The analytical developments are illustrated using centroid configurations. Then, deviations from the previous approach due to the nonzero device areas are studied and evaluated

Behavioral modeling of PWL analog circuits using symbolic analysis

Behavioral models are used both for top-down design and for bottom-up verification. During top-down design, models are created that reflect the nominal behavior of the different analog functions, as well as the constraints imposed by the parasitics. In this scenario, the availability of symbolic modeling expressions enable designers to get insight on the circuits, and reduces the computational cost of design space exploration. During bottom-up verification, models are created that capture the topological and constitutive equations of the underlying devices into behavioral descriptions. In this scenario symbolic analysis is useful because it enables to automatically obtain these descriptions in the form of equations. This paper includes an example to illustrate the use of symbolic analysis for top-down design.Comisión Interministerial de Ciencia y Tecnología TIC97-058

Geometrically-constrained, parasitic-aware synthesis of analog ICs

In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.Ministerio de Educación y Ciencia TEC2004-0175

Current-mode piecewise-linear function generators

We present a systematic design technique for current-mode piecewise-linear (PWL) function generators. It uses two building blocks: a high-resolution current rectifier, and a programmable current amplifier. We show how to arrange these blocks to obtain basic non-linearities from which generic characteristics are built through aggregations. Measurements from a 1.0 /spl mu/m CMOS prototype chip show 10 pA resolution in the rectification operation and 0.6% non-linearity errors in the programmable scaling operation for 2 /spl mu/A input current range