Robust symmetric multiplication for programmable analog VLSI array processing

This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs.Office of Naval Research (USA) N-00014- 02-1-0884Ministerio de Ciencia y Tecnología TIC2003-09817-C02-0

A Focal-Plane Image Processor for Low Power Adaptive Capture and Analysis of the Visual Stimulus

Portable applications of artificial vision are limited by the fact that conventional processing schemes fail to meet the specifications under a tight power budget. A bio-inspired approach, based in the goal-directed organization of sensory organs found in nature, has been employed to implement a focal-plane image processor for low power vision applications. The prototype contains a multi-layered CNN structure concurrent with 32times32 photosensors with locally programmable integration time for adaptive image capture with on-chip local and global adaptation mechanisms. A more robust and linear multiplier block has been employed to reduce irregular analog wave propagation ought to asymmetric synapses. The predicted computing power per power consumption, 142MOPS/mW, is orders of magnitude above what rendered by conventional architectures

Simplified state update calculation for fast and accurate digital emulation of CNN dynamics

Compared to other one-step integration methods, the 4th-order Runge-Kutta is much more accurate while still consisting in a rather reduced algorithmic structure. However, in terms of the computing power, it is more expensive than others. While the Forward Euler's method updates the state variable with a single evaluation of the derivative, 4th-order Runge-Kutta's method requires four. This is the reason why, when simulation speed is a central matter, e. g. in the digital emulation of CNN dynamics, the speed-accuracy trade-off is resolved in favour of the simpler, though less accurate, methods. A workaround for the computationally intensive calculation of the state variable update can be found for certain CNN models. If a FSR CNN model is employed, where the state variable is not allowed to go beyond the limits of the linear region of the cell output characteristic, the output can be identified with the state. In these conditions, and having linear templates, the update of the state variable can be computed, for a 4th-order Runge-Kutta's method, with a single function evaluation. It means that a digital emulation of the CNN dynamics following this method is as light-weighted as a Forward Euler's integrator, but much more accurate.Junta de Andalucía 2006-TIC-235

Programmable retinal dynamics in a CMOS mixed-signal array processor chip

The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully modelled by a Cellular Neural Network, whose evolution can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of the focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. For these reasons, a programmable array processor prototype chip has been designed and fabricated in a standard 0.5μm CMOS technology. The integrated system consists of a network of two coupled layers, containing 32 × 32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnections weights. Propagative, active wave phenomena and retina-like effects can be observed in this chip. Design challenges, trade-offs, the buildings blocks and some test results are presented in this paper.Office of Naval Research (USA) N00014-00-10429European Community IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

CMOS realization of a 2-layer CNN universal machine chip

Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically coupled layers of locally connected elementary nonlinear processors. In order to explore the possibilities of these complex spatio-temporal dynamics in image processing, a prototype chip has been developed by implementing this CNN model with analog signal processing blocks. This chip has been designed in a 0.5/spl mu/m CMOS technology. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5 /spl times/ 10/sup 6/ transistors, most of them operating in analog mode) are presented in this paper.Office of Naval Research (USA) N-00014-00-1-0429Comisión Interministerial de Ciencia y Tecnología TIC-1999-082

Diseño, intervención y propuesta de mejora para trabajar la coeducación en Educación Primaria

El Trabajo Fin de Grado que se muestra a continuación es una propuesta de intervención sobre “Coeducación”. Se trata de un tema que está a la orden del día, debido a la desigualdad entre hombres y mujeres existente en la sociedad. Se pretende fomentar la igualdad de género en las aulas para que en el futuro tengan un concepto diferente respecto al tema. En este proyecto el alumnado aprenderá el significado del concepto coeducación y todo lo que implica. La propuesta ha sido llevada a cabo con niños y niñas de 5º de Primaria de tres centros educativos de distintas zonas de Sevilla. En la presenta investigación se indican las actividades realizadas y las ideas de los discentes, así como un análisis de las mismas acompañado de sus respectivas conclusiones y propuestas de mejora.Universidad de Sevilla. Grado en Educación Primari

Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics

A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the natural visual pathway which renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 /spl mu/m CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5/spl times/10/sup 6/ transistors, most of them operating in analog mode) are presented in this paper.Comisión Interministerial de Ciencia y Tecnología TIC1999-082

Necrophiliac behaviour of Epidalea calamita in Sierra Norte de Sevilla Natural Park, SW Spain

En esta nota describimos un comportamiento necrofílico en sapo corredor (Epidalea cala- mita) relacionado con una depredación, posiblemente de nutria. En ella, discutimos las implicaciones de este fenómeno y sus posibles implicaciones reproductivas cómo se ha descrito en otros trabajos

Revalorization of Grape Seed Oil for Innovative Non-Food Applications

Grape processing produces a substantial amount of residues that are highly polluting and expensive to treat, being grape seed one of the main by-products with high commercial interest. During the extraction process of grape seed oil, most of the nutraceutical compounds remain on the solid cake. This book chapter resumes the potential utilization of grape seed oil for producing biobased materials through environmentally friendly processes that could substitute petroleum-derived products. Special attention is given to transesterification and epoxidation processes. The transesterification of grape seed oil in presence of methanol drives to the production of a biodiesel with excellent low-temperature properties. According to EN 14214, grape seed oil-based biodiesel presents a slightly lower cetane number than the specified limit. In addition, this biodiesel presents a low oxidation stability which can be improved by the incorporation of oxidation stabilizer. Attending to the epoxidation of grape seed oil, short reaction times and high temperatures are advised. Epoxidized grape seed oil can be used for the synthesis of biobased polyols and its further application on the synthesis of polyurethane compounds