The Front End Design of a Health Monitoring System

Abstract. In this paper an efficient e-health platform based on a low-cost sensor controller system is presented, exhibiting enhanced key characteristics able to provide broad coverage of medical scenarios in a reliable and flexible way. The heart of the system is a low-cost sensor controller capable of performing both simple medical tests and more advanced ones communicating with a Gateway and a tablet or smart phone providing instructions to the patient. Equipped with a simple and flexible communication protocol for data and command exchange, the developed platform is capable of readily supporting a variety of sensors with different sampling profiles. Furthermore, first promising results of on-going work pave the way for achieving considerable enhancement of sensors' accuracy (close to high-cost commercial ones) and significant extension of platform's portability through power consumption minimization. These characteristics have been verified by experimenting with various medical scenarios one of which is demonstrated here in detail

Architectures and implementation of error correcting codes

Due to the amazing performance of Turbo codes close to the fundamental Shannon limit, modern telecommunication standards have adopted this efficient scheme of channel coding for the reliability improvement during the data transmission and the appropriate use of the provided bandwidth. Therefore, their incorporation into a wide range of applications demands efficient architectures and implementations of high-throughput and low energy consumption in the case of the extremely complex and time consuming procedure of iterative decoding. Recent analog implementations of small iterative decoders exploit the nonlinear nature of transistors used in CMOS or BiCMOS technologies and outperform their digital counterparts in terms of power consumption and decoding speed. However, the use of these silicon technologies for the analog decoder’s implementation is incapable to cope with the particular specifications and demands of high-speed and high-performance telecom applications like optical communications and systems of magnetic storage. The present dissertation studies the use of SiGe BiCMOS technology in analog architectures for the implementation of high-throughput and moderate power consumption Turbo decoders. The design is based on Heterojunction Bipolar Transistors and leads to a significant increment of the analog system’s speed in contrast to the designs based on conventional bipolar transistors or MOS transistor, which operate in the subthreshold region in order to conform to the translinear principle. A generic methodology, using factor-graphs for the specification procedure of error control systems, is also presented. Furthermore, we map the derived specification onto the appropriate a circuit topology taking into account the characteristics of the SiGe BiCMOS technology. Finally, the methodology leads to an efficient design and consistent integration of high-speed analog decoders. We report useful conclusions for the adoption of the proposed methodology, and the use of Silicon-Germanium technology by presenting the first successful implementation of an analog Trellis decoder, and the simulation results of the relevant Turbo decoder in a 0.35μm AMS SiGe BiCMOS technology. The analog Trellis decoder (including I/O interfaces) exhibits the highest decoding speed reported till now and proves that Silicon-Germanium technology, in contrast to CMOS technology, is one of the most suitable and low-cost technologies for the implementation of high-speed analog decoder that can be embedded in telecom systems of particular high-throughput.Απόρροια της εκπληκτικής αποδόσεως των κωδίκων Turbo, η οποία προσεγγίζει το θεμελιώδες όριο του Shannon, είναι η υιοθέτησή τους από τα σύγχρονα τηλεπικοινωνιακά πρότυπα ως το αποτελεσματικότερο σχήμα κωδικοποίησης διαύλου για τη βελτίωση της αξιοπιστίας στη μετάδοση δεδομένων και την καλύτερη εκμετάλλευση του παρερχομένου εύρους ζώνης. Επομένως, η ενσωμάτωσή τους σε ένα ευρύ φάσμα εφαρμογών απαιτεί αποδοτικές αρχιτεκτονικές και υλοποιήσεις υψηλού ρυθμού διεκπεραίωσης και χαμηλής κατανάλωσης ενέργειας όσον αφορά την εξαιρετικά πολύπλοκη και χρονοβόρα επαναληπτική αποκωδικοποίησή τους. Οι πρόσφατες αναλογικές υλοποιήσεις μικρού μεγέθους επαναληπτικών αποκωδικοποιητών εκμεταλλεύονται την μη γραμμικότητα της φύσης του τρανζίστορ στις τεχνολογίες υλικού CMOS ή συμβατικής BiCMOS και πλεονεκτούν έναντι των αντίστοιχων υλοποιήσεων ψηφιακού υλικού, τόσο ως προς την κατανάλωση ισχύος, όσο και ως προς την ταχύτητα της αποκωδικοποίησης. Εντούτοις, η χρήση των τεχνολογιών αυτών Πυριτίου για την υλοποίηση αναλογικών αποκωδικοποιητών, με στόχο την εφαρμογή τους σε τηλεπικοινωνιακά συστήματα, όπως τα συστήματα οπτικών τηλεπικοινωνιών και αποθήκευσης μαγνητικού μέσου, τα οποία διακρίνονται για τον υψηλό ρυθμό διεκπεραίωσης και απόδοσης, αδυνατεί να ανταποκριθεί πλήρως στις ιδιαίτερες αυτές προδιαγραφές και απαιτήσεις. Η παρούσα διδακτορική διατριβή μελετά την χρήση της τεχνολογίας Πυριτίου-Γερμανίου (SiGe) BiCMOS σε αναλογικές αρχιτεκτονικές για την υλοποίηση αποκωδικοποιητών Turbo υψηλού ρυθμού διεκπεραίωσης και όσο το δυνατόν χαμηλής κατανάλωσης ισχύος. Η σχεδίαση βάσει των διπολικών τρανζίστορ ετεροεπαφής προσδίδει ιδιαίτερα υψηλή ταχύτητα στην απόκριση του αναλογικού συστήματος σε αντίθεση με τα συμβατικά διπολικά τρανζίστορ ή με τα τρανζίστορ πεδίου MOS, τα οποία λειτουργούν στην περιοχή υποκατωφλίου για τη διατήρηση της διαγραμμικής αρχής. Στα πλαίσια της διατριβής αυτής παρουσιάζεται μια γενική μεθοδολογία χρησιμοποιώντας τους γράφους παραγόντων για την προδιαγραφή συστημάτων ελέγχου λαθών. Έπειτα, πραγματοποιείται η σύζευξη της επιτευχθείσας προδιαγραφής με την κυκλωματική συμπεριφορά των τοπολογιών λαμβάνοντας υπ’ όψιν φυσικά τα χαρακτηριστικά της τεχνολογίας SiGe BiCMOS και καταλήγουμε στην αποδοτική σχεδίαση και ολοκλήρωση αποκωδικοποιητών διόρθωσης λαθών υψηλής ταχύτητας. Χρήσιμα συμπεράσματα, για την υιοθέτηση της προτεινόμενης μεθοδολογίας και τη χρήση της τεχνολογίας Πυριτίου-Γερμανίου, αναφέρονται με την παρουσίαση της πρώτης επιτυχούς υλοποίησης σε τεχνολογία 0.35μm AMS SiGe BiCMOS ενός αναλογικού Trellis αποκωδικοποιητή και των εξομοιωτικών αποτελεσμάτων του αντίστοιχου αποκωδικοποιητή Turbo, ο οποίος ενσωματώνει τον παραπάνω Trellis αποκωδικοποιητή. O αποκωδικοποιητής Trellis (συμπεριλαμβανομένου και τις διεπαφές εισόδου και εξόδου) παρουσιάζει την υψηλότερη ταχύτητα αποκωδικοποίησης μέχρι σήμερα και αποδεικνύει πως η τεχνολογία Πυριτίου-Γερμανίου είναι μια από τις πιο κατάλληλες και εξίσου χαμηλού κόστους τεχνολογίες σε σχέση με τις CMOS για την υλοποίηση αναλογικών αποκωδικοποιητών όσον αφορά τη δυνατότητα ενσωμάτωσής τους σε επικοινωνιακά συστήματα υψηλής ταχύτητας μετάδοσης δεδομένων

On the Design of Low-Cost IoT Sensor Node for e-Health Environments

The proliferation of Internet of Things (IoT) devices for patient monitoring has gained much attention in clinical care performance, proficient chronic disease management, and home caregiving. This work presents the design of efficient medical IoT sensor nodes (SNs) in terms of low-cost, low power-consumption, and increased data accuracy based on open-source platforms. The method utilizes a Sensor Controller (SC) within the IoT SN, which is capable of performing medical checks supporting a broad coverage of medical uses. A communication protocol has been developed for data and command exchange among SC, local gateways, and physicians’ or patients’ mobile devices (tablets, smart phones). The SC supports moving average window (MAW) and principle component analysis (PCA) filtering algorithms to capture data from the attached low-cost body sensors of different sampling profiles. Significant extensions in SN’s portability is achieved through energy consumption minimization based on the idle time gaps between sensors’ activations. SN’s components are either deactivated or set to low activity operation during these idle intervals. A medical case study is presented and the evaluated results show that the proposed SN can be incorporated into e-health platforms since it achieves comparable accuracy to its certified and high-cost commercial counterparts

Operational State Recognition of a DC Motor Using Edge Artificial Intelligence

Edge artificial intelligence (EDGE-AI) refers to the execution of artificial intelligence algorithms on hardware devices while processing sensor data/signals in order to extract information and identify patterns, without utilizing the cloud. In the field of predictive maintenance for industrial applications, EDGE-AI systems can provide operational state recognition for machines and production chains, almost in real time. This work presents two methodological approaches for the detection of the operational states of a DC motor, based on sound data. Initially, features were extracted using an audio dataset. Two different Convolutional Neural Network (CNN) models were trained for the particular classification problem. These two models are subject to post-training quantization and an appropriate conversion/compression in order to be deployed to microcontroller units (MCUs) through utilizing appropriate software tools. A real-time validation experiment was conducted, including the simulation of a custom stress test environment, to check the deployed models’ performance on the recognition of the engine’s operational states and the response time for the transition between the engine’s states. Finally, the two implementations were compared in terms of classification accuracy, latency, and resource utilization, leading to promising results

Pilot-Less Time Synchronization for OFDM Systems: Application to Power Line Receivers

Power line networks provide high-speed broadband communications without the need for new wirings. However, these networks present a hostile environment for high-speed data communications. The most common modulation method used in such systems is OFDM, since it copes effectively with noise, multipath, fading selectivity, and attenuation. A potential drawback of OFDM is its sensitivity to receiver synchronization imperfections, such as timing and sampling frequency offsets. Although several approaches have been proposed for estimating the time and frequency offset, they are based on the use of pilot sequences that are not available in power line communication standards. More importantly, they focus on isolated algorithms for compensating either time or frequency offsets without providing a complete, low complexity, OFDM receiver architecture that mitigates jointly time and frequency errors. This paper focuses on providing an OFDM receiver architecture that can be compatible with many power line standards. Extensive simulation studies show under realistic channel and noise conditions that the proposed receiver provides enhanced robustness to synchronization imperfections as compared to conventional approaches

Design of embedded systems with complex task dependencies and shared resource interference (Short Paper)

International audienceLanguages for embedded systems ensure predictable timing behavior by specifying constraints based on either data streaming or reactive control models of computation. Moreover, various toolsets facilitate the incremental integration of application functionalities and the system design by evolutionary refinement and model-based code generation. Modern embedded systems involve various sources of interference in shared resources (e.g. multicores) and advanced real-time constraints , such as mixed-criticality levels. A sufficiently expressive model-ing approach for complex dependency patterns between real-time tasks is needed along with a formal analysis of models for runtime resource managers with timing constraints. Our approach utilizes a model of computation , called Fixed-Priority Process Networks, which ensures functional determinism by unifying streaming and reactive control within a timed automata framework. The tool flow extends the open source TASTE tool-suite with model transformations to the BIP language and code generation tools. We outline the use of our flow on the design of a spacecraft on-board application running on a quad-core LEON4FT processor