Heavy p-type carbon doping of MOCVD GaAsP using CBrCl₃

CBrCl₃ is shown to be a useful precursor for heavy p-type carbon doping of GaAsxP1−x grown via metalorganic chemical vapor deposition (MOCVD) across a range of compositions. Structural and electrical properties of the GaAsP films were measured for various processing conditions. Use of CBrCl3 decreased the growth rate of GaAsP by up to 32% and decreases x by up to 0.025. The dependence of these effects on precursor inputs is investigated, allowing C-doped GaAsP films to be grown with good thickness and compositional control. Hole concentrations of greater than 2×10¹⁹ cm−3 were measured for values of x from 0.76 to 0.90.National Science Foundation (U.S.) (Award 0939514)National Research Foundation of SingaporeNational Science Foundation (U.S.) (Award DMR-14-19807

GaAsP/InGaP heterojunction bipolar transistors grown by MOCVD

Heterojunction bipolar transistors with GaAs[subscript x]P[subscript 1−x] bases and collectors and In[subscript y]Ga[subscript 1−y]P emitters were grown on GaAs substrates via metalorganic chemical vapor deposition, fabricated using conventional techniques, and electrically tested. Four different GaAs[subscript x]P[subscript 1−x] compositions were used, ranging from x = 0.825 to x = 1 (GaAs), while the In[subscript y]Ga[subscript 1−y]P composition was adjusted to remain lattice-matched to the GaAsP. DC gain close to or exceeding 100 is measured for 60 μm diameter devices of all compositions. Physical mechanisms governing base current and therefore current gain are investigated. The collector current is determined not to be affected by the barrier caused by the conduction band offset between the InGaP emitter and GaAsP base. While the collector current for the GaAs/InGaP devices is well-predicted by diffusion of electrons across the quasi-neutral base, the collector current of the GaAsP/InGaP devices exceeds this estimate by an order of magnitude. This results in higher transconductance for GaAsP/InGaP than would be estimated from known material properties.National Science Foundation (U.S.) (Award 0939514

SiGe-On-Insulator (SGOI) Technology and MOSFET Fabrication

In this work, we have developed two different fabrication processes for relaxed Si₁₋xGex-on-insulator (SGOI) substrates: (1) SGOI fabrication by etch-back approach, and (2) by "smart-cut" approach utilizing hydrogen implantation. Etch-back approach produces SGOI substrate with less defects in SiGe film, but the SiGe film uniformity is inferior. "Smart-cut" approach has better control on the SiGe film thickness and uniformity, and is applicable to wider Ge content range of the SiGe film. We have also fabricated strained-Si n-MOSFET’s on SGOI substrates, in which epitaxial regrowth was used to produce the surface strained Si layer on relaxed SGOI substrate, followed by large-area n-MOSFET’s fabrication on this structure. The measured electron mobility shows significant enhancement (1.7 times) over both the universal mobility and that of co-processed bulk-Si MOSFET’s. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si₁₋xGex layer.Singapore-MIT Alliance (SMA

Microstructure and conductance-slope of InAs/GaSb tunnel diodes

InAs/GaSb and similar materials systems have generated great interest as a heterojunction for tunnel field effect transistors (TFETs) due to favorable band alignment. However, little is currently understood about how such TFETs are affected by materials defects and nonidealities. We present measurements of the conductance slope for various InAs/GaSb heterojunctions via two-terminal electrical measurements, which removes three-terminal parasitics and enables direct study on the effect of microstructure on tunnelling. Using this, we can predict how subthreshold swings in TFETs can depend on microstructure. We also demonstrate growth and electrical characterization for structures grown by metalorganic chemical vapor deposition (MOCVD)—a generally more scalable process compared with molecular beam epitaxy (MBE). We determine that misfit dislocations and point defects near the interface can lead to energy states in the band-gap and local band bending that result in trap-assisted leakage routes and nonuniform band alignment across the junction area that lower the steepness of the conductance slope. Despite the small lattice mismatch, misfit dislocations still form in InAs on GaSb due to relaxation as a result of large strain from intermixed compositions. This can be circumvented by growing GaSb on InAs, straining the GaSb underlayer, or lowering the InAs growth temperature in the region of the interface. The conductance slope can also be improved by annealing the samples at higher temperatures, which we believe acts to annihilate point defects and average out major fluctuations in band alignment across the interface. Using a combination of these techniques, we can greatly improve the steepness of the conductance slope which could result in steeper subthreshold swings in TFETs in the future.National Science Foundation (U.S.). Center for Energy Efficient Electronics Science (Award 0939514)Natural Sciences and Engineering Research Council of Canada (Postgraduate M Scholarship

Graded InGaN Buffers for Strain Relaxation in GaN/InGaN Epliayers Grown on Sapphire

Graded InGaN buffers are employed to relax the strain arising from the lattice and thermal mismatches between GaN/InGaN epilayers grown on sapphire. The formation of V-pits in linearly graded InGaN/GaN bulk epilayers is illustrated. The V-pits were sampled using Atomic Force Microscopy and Scanning Electron Microscopy to examine their variation from the theoretical geometry shape. We discovered that the size of the V-pit opening in linearly graded InGaN, with and without GaN cap layer, has a Gaussian distribution. As such, we deduce that the V-pits are produced at different rates, as the growth of the InGaN layer progresses. In Stage I, the V-pits form at a slow rate at the beginning and then accelerate in Stage II when a critical thickness is reached before decelerating in Stage III after arriving at a mean size. It is possible to fill the V-pits by growing a GaN cap layer. It turns out that the filling of the V-pits is more effective at lower growth temperature of the GaN cap layer and the size of the V-pits opening, which is continued in to GaN cap layer, is not dependent on the GaN cap layer thickness. Furthermore, graded InGaN/GaN layers display better strain relaxation as compared to conventionally grown bulk GaN. By employing a specially design configuration, the V-pits can be eliminated from the InGaN epilayer.Singapore-MIT Alliance (SMA

Graded InGaN Buffers for Strain Relaxation in GaN/InGaN Epilayers Grown on sapphire

Graded InGaN buffers were employed to relax the strain arising from the lattice and thermal mismatch in GaN/InGaN epilayers grown on sapphire. An enhanced strain relaxation was observed in GaN grown on a stack of five InGaN layers, each 200 nm thick with the In content increased in each layer, and with an intermediate thin GaN layer, 10 nm thick inserted between the InGaN layers, as compared to the conventional two-step growth of GaN epilayer on sapphire. The function of the intermediate layer is to progressively relax the strain and to annihilate the dislocations that build up in the InGaN layer. If the InGaN layers were graded too rapidly, more dislocations will be generated. This increases the probability of the dislocations getting entangled and thereby impeding the motion of the dislocations to relax the strain in the InGaN layer. The optimum growth conditions of the intermediate layer play a major role in promoting the suppression and filling of the V-pits in the GaN cap layer, and were empirically found to be a thin 10 nm GaN grown at 750 0°C and annealed at 1000 0°C.Singapore-MIT Alliance (SMA

Fabrication of Two-Dimensional Photonic Crystals in AlGaInP/GaInP Membranes by Inductively Coupled Plasma Etching

The fabrication process of two-dimensional photonic crystals in an AlGaInP/GaInP multi-quantum-well membrane structure is developed. The process includes high resolution electron-beam lithography, pattern transfer into SiO₂ etch mask by reactive ion etching, pattern transfer through AlGaInP/GaInP layer by inductively coupled plasma (ICP) etching and a selective undercut wet etch to create the freestanding membrane. The chlorine-based ICP etching conditions are optimized to achieve a vertical sidewall. The photonic crystal structures with periods of a=160-480nm are produced.Singapore-MIT Alliance (SMA

Fabrication and I-V Characterization of ZnO Nanorod Based Metal-Insulator-Semiconductor Junction

We report on the characteristics of a ZnO based metal insulator semiconductor (MIS) diode comprised of a heterostructure of n-ZnO nanorods/n-GaN. The MIS structure consisted of unintentional - doped n type ZnO nanorods grown on n-GaN sample using hydrothermal synthesis at low temperature (100°). The ZnO nanorod layer was vertically grown from the GaN sample, having the diameter 100nm and length 2µm. Then, an insulator layer for electrical isolation was deposited on the top of ZnO nanorod layer by using spin coating method. A metal layer (gold) was finally deposited on the top. The I-V dependences show a rectifying diode like behavior with a leakage current of 2.10⁻⁵ A and a threshold voltage of about 3V. Depend on the thickness of the insulator, the I-V dependences of the n-ZnO/n-GaN heterostructure was varied from rectifying behavior to Ohmic and nearly linear.Singapore-MIT Alliance (SMA