Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

SPRAY PYROLYSIS DEPOSITION FOR GAS SENSOR INTEGRATION IN THE BACKEND OF STANDARD CMOS PROCESSES

ABSTRACT Gas sensors are based on metal oxides, which likely will have a considerable impact on future smart phones, are analyzed by means of simulations. The deposition of a thin tin oxide film at the backend of a CMOS process has enabled the manufacture of integrated gas sensors. A spray pyrolysis technique is implemented for the deposition step, resulting in a thin tin oxide layer with good step coverage and uniformity. A simulation approach for spray pyrolysis deposition is presented, along with a discussion of the gas sensor operation. A sample model for H2 detection is suggested, while our research serves as a step to link the simulation of gassensitive material deposition and gas sensor operation

The Role of Thermalization in the Cooling Dynamics of Hot Carrier Solar Cells

The hot carrier solar cell (HCSC) concept has been proposed to overcome the Shockley Queisser limit of a single p–n junction solar cell by harvesting carriers before they have lost their surplus energy. A promising family of materials for these purposes is metal halide perovskites (MHP). MHPs have experimentally shown very long cooling times, the key requirement of a HCSC. By using ensemble Monte Carlo simulations, light is shed on why cooling times are found to be extended. This article concentrates on the role of thermalization in the cooling process. The role of carrier–phonon and carrier–carrier interactions in thermalization and cooling is specified, while showing how these processes depend on material parameters, such as the dielectric constant and effective mass. It is quantified how thermalization acts as a cooling mechanism via the cold background effect. The importance of a low degree of background doping is to achieve the observed extended cooling times. Herein, it is mapped out how perovskites should be tuned, their material parameters, carrier concentration, and purity, in order to realize a HCSC. It contributes to the debate on the cooling times in MHPs and the suitability of tin perovskites for HCSCs.</p

Topography simulation of novel processing techniques

Zsfassung in dt. SpracheTopographiesimulationen ermöglichen eine Visualisierung der Waferoberfläche und der Materialschichten eines Bauelements nachdem ein oder mehrere Prozesse durchlaufen worden sind. Weit verbreitete Prozesstechniken, wie Ätzen oder Abscheiden neuer Materialschichten, wurden jahrzehntelang erforscht und hoch komplexe Modelle existieren bereits. Durch die Level Set-Methode ist es möglich die Veränderung der Topographie darzustellen. Um dem Mooreschen Gesetz gerecht zu werden, werden ständig neue Prozesstechniken entwickelt, die eine Miniaturisierung möglich machen und gleichzeitig die Produktionskosten niedrig halten.Das Verständnis von neuen Prozesstechnologien wird durch die Anwendung von Topographiesimulationen verbessert. Die lokale anodische Oxidation von Siliziumoberflächen mit Hilfe eines Rasterkraftmikroskops ist eine Methode zur Erzeugung nanometergroßer Muster mit einer geladenen Nadel.Diese Technologie wurde entwickelt, um die Grenzen der Fotolithographie bei der fortschreitenden Miniaturisierung zu überwinden. Im Rahmen dieser Arbeit wurde ein Modell entwickelt, das die Simulation von Topographieänderung bei der Anwendung der lokalen anodischen Oxidation ermöglicht. Die Topographieänderung wurde unter Verwendung der Monte Carlo-Methode modelliert, wobei die Partikelverteilung der Oberflächenladungsdichteverteilung folgt. Die Ladungsverteilung entsteht durch ein starkes elektrisches Feld zwischen der Rasterkraftmikroskopnadel und dem Siliziumwafer.Eine ähnliche Situation findet man auch bei EEPROM Speicherzellen, die nach derzeitigem Stand der Prozesstechnik nicht weiter miniaturisiert werden können. Aus diesem Grund werden dreidimensionale Strukturen eingeführt, die eine Erhöhung der Anzahl der verfügbaren Speicherzellen ermöglicht ohne dabei mehr Oberfläche zu beanspruchen. Für die Herstellung eines Ätzprofils hierzu wurde, im Rahmen dieser Arbeit, ein Ätzmodell für Bit Cost Scalable (BiCS) Speicherzellen im Level Set-Framework entwickelt.Weiters wurde ein Sprühpyrolyse-Abscheidungsmodell entwickelt und in das Level Set-Framework integriert. Diese Prozessmethode ermöglicht eine Abscheidung dünner Schichten, die unter anderem bei Solarzellen und Gassensoren Verwendung finden. Es wurden zwei Modelle für die Topographieänderung infolge des Sprühpyrolyse-Prozesses präsentiert, davon eines mit einem Elektro- und eines mit einem Druckzerstäuber. Das erste Modell beschreibt eine schichtweise Abscheidung einzelner Tröpfchen beim Aufprall auf den Wafer. Beim zweiten Modell verdampfen die Tröpfchen kurz vor dem Aufprall und ein CVD-ähnlicher Schichtzuwachs erfolgt.Topography simulations allow for a visualization of semiconductor surfaces as well as the interfaces between various material regions after a given processing step. Topography modeling of well-established processing techniques, such as material etching and deposition, has been studied for decades and very sophisticated models exist which envision the semiconductor surfaces and interfaces using the Level Set method. However, as the technology node shrinks along the predicted path of Moore's law, novel processing techniques are constantly introduced in order to enable miniaturization and to ease the financial burden of processing at these reduced nodes.The ability to simulate semiconductor wafer topographies after the application of newly-introduced process technologies can go a long way in understanding their potential. The local anodic oxidation of silicon surfaces with an atomic force microscope (AFM) is a method which produces nanosized patterns on a silicon wafer using a localized charged needle. The technology has been developed in order to tackle the limited miniaturization potential of current photolithographic techniques. In the scope of this work, a technique which models the changing silicon topography as the silicon dioxide pattern is applied to the wafer is introduced. The topography motion is simulated using a Monte Carlo technique, whereby a particle distribution follows the surface charge density distribution. The charge density arises from the application of a strong electric field between the AFM needle tip and the silicon wafer surface.Similarly, EEPROM memory cells can not be miniaturized further with the current processing techniques. Therefore, three-dimensional structures are being introduced in order to increase the number of available memory cells without increasing the area required. In the scope of this work, a model for Bit Cost Scalable (BiCS) memory hole etching is implemented in a Level Set framework as a combination of silicon and silicon dioxide etching steps.A spray pyrolysis deposition model is also developed and implemented within the Level Set framework. This processing technique enables the deposition of thin films for applications such as gas sensors and solar cells. Two models for the topography modification due to spray pyrolysis deposition are presented, with an electric and a pressure atomizing nozzle. The resulting film growth is modeled as a layer by layer deposition of the individual droplets which reach the wafer surface or as a CVD-like process, depending on whether the droplets form a vapor near the interface or if they deposit a film only after surface collision.17

Editorial for the Special Issue on Miniaturized Transistors

Complementary Metal Oxide Semiconductor (CMOS) devices and fabrication techniques have enabled tremendous technological advancements in a short period of time [...

Thermo-Electro-Mechanical Simulation of Semiconductor Metal Oxide Gas Sensors

There is a growing demand in the semiconductor industry to integrate many functionalities on a single portable device. The integration of sensor fabrication with the mature CMOS technology has made this level of integration a reality. However, sensors still require calibration and optimization before full integration. For this, modeling and simulation is essential, since attempting new, innovative designs in a laboratory requires a long time and expensive tests. In this manuscript we address aspects for the modeling and simulation of semiconductor metal oxide gas sensors, devices which have the highest potential for integration because of their CMOS-friendly fabrication capability and low operating power. We analyze recent advancements using FEM models to simulate the thermo-electro-mechanical behavior of the sensors. These simulations are essentials to calibrate the design choices and ensure low operating power and improve reliability. The primary consumer of power is a microheater which is essential to heat the sensing film to appropriately high temperatures in order to initiate the sensing mechanism. Electro-thermal models to simulate its operation are presented here, using FEM and the Cauer network model. We show that the simpler Cauer model, which uses an electrical circuit to model the thermo-electrical behavior, can efficiently reproduce experimental observations

Special Issue on Miniaturized Transistors, Volume II

Due to the great success of the initial Special Issue on Miniaturized Transistors [...

Performance and Stress Analysis of Metal Oxide Films for CMOS-Integrated Gas Sensors

The integration of gas sensor components into smart phones, tablets and wrist watches will revolutionize the environmental health and safety industry by providing individuals the ability to detect harmful chemicals and pollutants in the environment using always-on hand-held or wearable devices. Metal oxide gas sensors rely on changes in their electrical conductance due to the interaction of the oxide with a surrounding gas. These sensors have been extensively studied in the hopes that they will provide full gas sensing functionality with CMOS integrability. The performance of several metal oxide materials, such as tin oxide (SnO2), zinc oxide (ZnO), indium oxide (In2O3) and indium-tin-oxide (ITO), are studied for the detection of various harmful or toxic cases. Due to the need for these films to be heated to temperatures between 250°C and 550°C during operation in order to increase their sensing functionality, a considerable degradation of the film can result. The stress generation during thin film deposition and the thermo-mechanical stress that arises during post-deposition cooling is analyzed through simulations. A tin oxide thin film is deposited using the efficient and economical spray pyrolysis technique, which involves three steps: the atomization of the precursor solution, the transport of the aerosol droplets towards the wafer and the decomposition of the precursor at or near the substrate resulting in film growth. The details of this technique and a simulation methodology are presented. The dependence of the deposition technique on the sensor performance is also discussed

Editorial for the Special Issue on Miniaturized Transistors

Complementary Metal Oxide Semiconductor (CMOS) devices and fabrication techniques have enabled tremendous technological advancements in a short period of time [...

Application of Two-Dimensional Materials towards CMOS-Integrated Gas Sensors

During the last few decades, the microelectronics industry has actively been investigating the potential for the functional integration of semiconductor-based devices beyond digital logic and memory, which includes RF and analog circuits, biochips, and sensors, on the same chip. In the case of gas sensor integration, it is necessary that future devices can be manufactured using a fabrication technology which is also compatible with the processes applied to digital logic transistors. This will likely involve adopting the mature complementary metal oxide semiconductor (CMOS) fabrication technique or a technique which is compatible with CMOS due to the inherent low costs, scalability, and potential for mass production that this technology provides. While chemiresistive semiconductor metal oxide (SMO) gas sensors have been the principal semiconductor-based gas sensor technology investigated in the past, resulting in their eventual commercialization, they need high-temperature operation to provide sufficient energies for the surface chemical reactions essential for the molecular detection of gases in the ambient. Therefore, the integration of a microheater in a MEMS structure is a requirement, which can be quite complex. This is, therefore, undesirable and room temperature, or at least near-room temperature, solutions are readily being investigated and sought after. Room-temperature SMO operation has been achieved using UV illumination, but this further complicates CMOS integration. Recent studies suggest that two-dimensional (2D) materials may offer a solution to this problem since they have a high likelihood for integration with sophisticated CMOS fabrication while also providing a high sensitivity towards a plethora of gases of interest, even at room temperature. This review discusses many types of promising 2D materials which show high potential for integration as channel materials for digital logic field effect transistors (FETs) as well as chemiresistive and FET-based sensing films, due to the presence of a sufficiently wide band gap. This excludes graphene from this review, while recent achievements in gas sensing with graphene oxide, reduced graphene oxide, transition metal dichalcogenides (TMDs), phosphorene, and MXenes are examined