Development of a serial powering scheme and a versatile characterization system for the ATLAS pixel detector upgrade

In order to increase the probability of new discoveries the LHC will be upgraded to the HL-LHC. The upgrade of the ATLAS detector is an essential part of this program. The entire ATLAS tracking system will be replaced by an all-silicon detector called Inner Tracker (ITk) which should be able to withstand the increased luminosity. The work presented in this thesis is focused on the ATLAS ITk pixel detector upgrade. Advanced silicon pixel detectors will be an essential part of the ITk pixel detector where they will be used for tracking and vertexing. Characterization of the pixel detectors is one of the required tasks for a successful ATLAS tracker upgrade. Therefore, the work presented in this thesis includes the development of a versatile and modular test system for advanced silicon pixel detectors for the HL-LHC. The performance of the system is verified. Single and quad FE-I4 modules functionalities are characterized with the developed system. The reduction of the material budget of the ATLAS ITk pixel detector is essential for a successful operation at high luminosity. Therefore, a low mass, efficient power distribution scheme to power detector modules (serial powering scheme) is investigated as well in the framework of this thesis. A serially powered pixel detector prototype is built with all the components that are needed for current distribution, data transmission, sensor biasing, bypassing and redundancy in order to prove the feasibility of implementing the serial powering scheme in the ITk. Detailed investigations of the electrical performance of the detector prototype equipped with FE-I4 quad modules are made with the help of the developed readout system

The ATLAS Level-1 Topological Processor: Phase-I upgrade and Phase-II adaptation

The increased instantaneous luminosity of the LHC in Run 3 brings the need for the upgrade of the ATLAS trigger system. The new Phase-I L1Topo system, which replaces its Phase-0 predecessor, processes data from the Feature Extractors (FEXes) and the upgraded Muon to Central Trigger Processor Interface (MUCTPI) to perform topological and multiplicity triggers. The upgraded L1Topo system provides higher processing capabilities in order to make use of the improved input objects from the new FEXes and the MUCTPI. The L1Topo system consists of three ATCA modules, each hosting two processor FPGAs (Xilinx Ultrascale+ 9P). The L1Topo firmware is composed of a large number of sort/select, decision, and multiplicity algorithms, that are automatically assembled and configured based on the provided trigger menu. The parameters used for the algorithms can be set and changed via the IPBus by the Online Software during a Run. The topological trigger configuration is fully described in a single menu-driven json file, from which algorithm VHDL code, as well as IPbus address mapping, are automatically generated. For the HL-LHC, the Phase-I L1Topo system will be replaced by a Global Trigger, a time-multiplexed system, which concentrates the data of a full event into a single FPGA. In order to match the new operational environment, the fully synchronous, very low latency (new data arriving every 25 ns), parallel implementation (~ 2.5m LUTs) of the Phase-I Topological firmware is being adapted to a significantly higher latency budget (new data arriving every 1.2 us) and a substantially tighter resource budget (~ 100k LUTs). The main challenge is to allow for multiple working points of the utilized resources and latency for each algorithm – an essential requirement, since a significant difference in arrival times of the various input objects is expected. A detailed overview of the Phase-I L1Topo hardware and firmware is provided. Phase-II related firmware adaptations are also discussed

L1Topo: The Level-1 Topological Processor for ATLAS Phase-I upgrade and its firmware evolution for use within the Phase-II Global Trigger

The increased instantaneous luminosity of the LHC in Run 3 brings the need for the upgrade of the ATLAS trigger system. The newly commissioned Phase-I L1Topo system, which replaces its Phase-0 predecessor, processes data from the Feature Extractors (FEXes) and the upgraded Muon to Central Trigger Processor Interface (MUCTPI) to perform topological and multiplicity triggers. The L1Topo system consists of three ATCA modules, each hosting two processor FPGAs (Xilinx Ultrascale+ 9P). The L1Topo firmware is composed of a large number of sort/select, decision, and multiplicity algorithms, that are automatically assembled and configured based on the provided trigger menu. For the HL-LHC, the Phase-I L1Topo system will be replaced by a Global Trigger, a time-multiplexed system, which concentrates the data of a full event into a single FPGA. In order to match the new operational environment, the fully synchronous, very low latency (new data arriving every 25 ns), parallel implementation (~2.5m LUTs) of the Phase-I Topological firmware is being adapted to a significantly higher latency budget (new data arriving every 1.2 us) and a substantially tighter resource budget (~100k LUTs). The main challenge is to allow for multiple working points of the utilized resources and latency for each algorithm. A detailed overview of the Phase-I L1Topo hardware and firmware is provided. Preliminary performance results achieved by the Phase-I L1Topo together with a description of the challenges found during the commissioning process are included. Phase-II related firmware adaptations are also discussed

L1Topo: The Level-1 Topological Processor for ATLAS Phase-I upgrade and its firmware evolution for use within the Phase-II Global Trigger

The increased instantaneous luminosity of the LHC in Run 3 brings the need for the upgrade of the ATLAS trigger system. The newly commissioned Phase-I L1Topo system, which replaces its Phase-0 predecessor, processes data from the Feature Extractors (FEXes) and the upgraded Muon to Central Trigger Processor Interface (MUCTPI) to perform topological and multiplicity triggers. The L1Topo system consists of three ATCA modules, each hosting two processor FPGAs (Xilinx Ultrascale+ 9P). The L1Topo firmware is composed of a large number of sort/select, decision, and multiplicity algorithms, that are automatically assembled and configured based on the provided trigger menu. For the HL-LHC, the Phase-I L1Topo system will be replaced by a Global Trigger, a time-multiplexed system, which concentrates the data of a full event into a single FPGA. In order to match the new operational environment, the fully synchronous, very low latency (new data arriving every 25 ns), parallel implementation (~2.5m LUTs) of the Phase-I Topological firmware is being adapted to a significantly higher latency budget (new data arriving every 1.2 us) and a substantially tighter resource budget (~100k LUTs). The main challenge is to allow for multiple working points of the utilized resources and latency for each algorithm. A detailed overview of the Phase-I L1Topo hardware and firmware is provided. Preliminary performance results achieved by the Phase-I L1Topo together with a description of the challenges found during the commissioning process are included. Phase-II related firmware adaptations are also discussed

Global Trigger Versatile Module for ATLAS Phase-II upgrade

ATLAS detector at the Large Hadron Collider (LHC) will undergo a major Phase-II upgrade for the High Luminosity LHC (HL-LHC). The upgrade affects all the main ATLAS systems including the Trigger and Data Acquisition. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the L0Calo trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module (GCM) as a building block of its design. An additional Global Trigger Versatile Module (GVM) has been designed according to the Global Trigger hardware specifications. To achieve a high input and output bandwidth and substantial processing power, both the GVM and the GCM host the most advanced FPGAs and optical modules, running at high data rates (up to 28 Gb/s) as well as other hardware resources needed for the Global Trigger. The GVM acts as an auxiliary hardware component that can be used for development, testing and operational purposes within and beyond the Global Trigger. The GVM is designed in an ATCA form factor with the possibility of a standalone operation. The main building blocks are the following: one large processing FPGA (Xilinx Ultrascale+ VU13P), up to eight Finisar BOA modules for real-time data path, one Finisar BOA module for interface to Front-End Link eXchange (FELIX) system, one UltraZed board with Zynq UltraScale+, one IPM Controller (IPMC), one FPGA power mezzanine and two DDR4 RAMs. In order to optimize the signal integrity for the high-speed signals, dedicated high-speed PCB design techniques, such as physical and spacing constraints, phase tuning, micro and buried vias, were used. Successful results demonstrating a good performance of the on-board components have been obtained. The poster will provide a hardware overview and measurement results of the GVM

Global Trigger Technological Demonstrator for ATLAS Phase-II upgrade

ATLAS detector at the Large Hadron Collider (LHC) will undergo a major Phase-II upgrade for the High Luminosity LHC (HL-LHC). The upgrade affects all major ATLAS systems, including the Trigger and Data Acquisition systems. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module (GCM) as a building block of its design. To achieve a high input and output bandwidth and substantial processing power, the GCM will host the most advanced FPGAs and optical modules. In order to evaluate the new generation of optical modules and FPGAs running at high data rates (up to 28 Gb/s), a Global Trigger Technological Demonstrator board has been designed and tested. The main hardware blocks of the board are the Xilinx Virtex Ultrascale+ 9P FPGA and a number of optical modules, including high-speed Finisar BOA and Samtec FireFly modules. Long-run link tests have been performed for the Finisar BOA and Samtec FireFly optical modules running at 25.65 and 27.58 Gb/s respectively. Successful results demonstrating a good performance of the optical modules when communicating with the FPGA have been obtained. The paper provides a hardware overview and measurement results of the Technological Demonstrator

Global Trigger Versatile Module for ATLAS Phase-II upgrade

The ATLAS detector at the Large Hadron Collider will undergo a major Phase-II upgrade for the High Luminosity LHC. The upgrade affects all the main ATLAS systems including the Trigger and Data Acquisition. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the L0Calo trigger objects and applies topological requirements. The Global Trigger uses an ATCA Global Common Module as a building block of its design. The additional, standalone, Global Trigger Versatile Module has been designed according to the Global Trigger hardware specifications. The Global Trigger Versatile Module acts as an auxiliary hardware component that can be used for development, testing and operational purposes within and beyond the Global Trigger in projects requiring high bandwidth and processing capabilities. The Global Trigger Versatile Module hosts an advanced Xilinx Ultrascale+ VU13P FPGA and Finisar BOA optical modules running at data rates up to 25.8 Gb/s, as well as other hardware resources needed for the Global Trigger, located on a high-density PCB, optimized for high-speed data transmission. The Global Trigger Versatile Module successfully passed a full testing program, including verification of the main hardware functionality of the module, performance evaluation of the high-speed optical modules and the FPGA, and Global Common Module development firmware tests. Successful results demonstrating a good performance of the on-board components have been obtained

Global Trigger Versatile Module for ATLAS Phase-II upgrade

The ATLAS detector at the Large Hadron Collider will undergo a major Phase-II upgrade for the High Luminosity LHC. The upgrade affects all the main ATLAS systems including the Trigger and Data Acquisition. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the L0Calo trigger objects and applies topological requirements. The Global Trigger uses an ATCA Global Common Module as a building block of its design. The additional, standalone, Global Trigger Versatile Module has been designed according to the Global Trigger hardware specifications. The Global Trigger Versatile Module acts as an auxiliary hardware component that can be used for development, testing and operational purposes within and beyond the Global Trigger in projects requiring high bandwidth and processing capabilities. To achieve a high input and output bandwidth and substantial processing power the Global Trigger Versatile Module hosts an advanced Xilinx Ultrascale+ VU13P FPGA and Finisar BOA optical modules, running at high data rates up to 25.8 Gb/s, as well as other hardware resources needed for the Global Trigger, located on a high-density PCB, optimized for high-speed data transmission. A testing program of the Global Trigger Versatile Module includes verification of the main hardware functionality of the module, performance evaluation of the high-speed optical modules and the FPGA, and Global Common Module development firmware tests. Successful results demonstrating a good performance of the on-board components have been obtained

The Prototype Hardware Design of Global Common Module for Global Trigger System of the ATLAS Phase-II Upgrade on HL-LHC

The HL-LHC [1] is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined (up to 4000 fb−1). Meeting these requirements poses significant challenges to the hardware design of Trigger and Data Acquisition system. A baseline architecture, based on a single-level hardware trigger with a maximum rate of 1 MHz and 10 µs latency, is proposed for ATLAS. The hardware-based Level-0 Trigger system is composed of the Level-0 Calorimeter Trigger (L0Calo) [2], the Level-0 Muon Trigger (L0Muon) [3], the Global Trigger [4] and the Central Trigger sub-systems [4]. The Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The calorimeter detector subsystems, FEXs [3], and MUCTPI [3] provide serial data for each bunch crossing to the MUX layer. These signals are then time-multiplexed [5] and the signals for a given event are transported to a single GEP node that executes the algorithms. The results are then sent to the CTP through the CTP Interface. The hardware implementation of the Global Trigger consists of three primary components: a Multiplexer Processor (MUX) layer, a GEP layer, and a demultiplexing Global-to-CTP Interface (CTP Interface), all of which have identical hardware composed of ATCA modules and FPGAs with many multi-gigabit transceivers. The single Global Common Module (GCM) hardware is implemented across the Global Trigger system, minimizing the complexity of the firmware and simplifying the system design and long-term maintenance