A Charge Pump Without Overstress For Standard Cmos Process With Improved Current Driver Capability

Many charge pump structures that overcome gate-oxide overstress have been proposed in the last few years. Though they differ in the number of phases and in efficiency, they have almost the same current driver capability. A new charge pump without gate-oxide overstress, with a better current driver capability is proposed here. The new circuit is derived from a two-phase charge pump in order to inherit its efficiency. A four-stage structure of the proposed circuit has shown a driver current capability 40% better than the previous solutions. The proposed circuit is also faster than the previous charge pumps that overcome gate-oxide overstress. © 2008 IEEE.618622Cruz, C.A.M., Filho, C.A.R., Mognon, V.R., A Charge Pump Circuit Without Gate-Oxide Overstress for Standard CMOS Technology and Suitable for Low-Power Applications these ProceedingsRecape, E., Dage, J.M., A PMOS-switch based charge pump, allowing lost cost implementation on a CMOS standard process (2005) Proc. ESSCIRC, pp. 77-80. , SeptPan, J., Yoshihara, T., A Charge Pump Circuit Without Overstress in Low-Voltage CMOS Standard Process (2007) IEEE Electron Devices and Solid-State, pp. 501-504. , DecCabrine, A., Gobbi, L., Torelli, G., Enhanced charge pump for ultra-low-voltage applications (2006) Electron. Lett, 42 (0), pp. 512-514. , AprilKer, M.D., Chen, S.L., Tsai, C.S., Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS process (2006) IEEE J. Solid-State Circuits, 41, pp. 1100-1107. , MayDickson, J.F., On-chip high voltage generation in MNOS integrated circuits using an improved voltage multiplier technique (1976) IEEE J. Solid State Circuits, pp. 374-378. , Ju

A Charge Pump Circuit Without Gate-oxide Overstress For Standard Cmos Technology And Suitable For Low-power Applications

In the last years the gate-oxide overstress has become a great concern for CMOS circuits and even more so for circuits such as charge pumps. A new charge pump circuit that overcomes the gate-oxide overstress problem and has improved efficiency is proposed in this work. Simulations have shown that for 1μA current load a four-stage structure of proposed circuit reaches efficiency of about 64%, what is almost three times the efficiency of previous solutions in the same conditions. The better efficiency makes this circuit more suitable for low-power applications. Measurements have shown that a four-stage structure of the new circuits yields a pumping efficiency of 98.12%. © 2008 IEEE.4650Dickson, J.F., On-chip high voltage generation in MNOS integrated circuits using an improved voltage multiplier technique (1976) IEEE J. Solid State Circuits, pp. 374-378. , JunPark, J.Y., Chung, Y., A Low-Voltage Charge Pump Circuit with High Pumping Efficiency in Standard CMOS Logic Process (2007) IEEE Electron Devices And Solid-State Circuits, pp. 317-320. , DecRecape, E., Dage, J.M., A PMOS-switch based charge pump, allowing lost cost implementation on a CMOS standard process (2005) Proc. ESSCIRC, pp. 77-80. , SeptPan, J., Yoshihara, T., A Charge Pump Circuit Without Overstress in Low-Voltage CMOS Standard Process (2007) IEEE Electron Devices and Solid-State, pp. 501-504. , DecKer, M.D., Chen, S.L., Tsai, C.S., Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS process (2006) IEEE J. Solid-State Circuits, 41, pp. 1100-1107. , MayLauterbach, C., Weber, W., Romer, D., Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps (2000) IEEE J. Solid-State Circuits, 35, pp. 719-723. , MayWu, E.Y., Power-law voltage acceleration: A key element for ultra-thin gate oxide reliability (2005) Microelectronics Reliability, 45, pp. 1809-1834Cabrine, A., Gobbi, L., Torelli, G., Enhanced charge pump for ultra-low-voltage applications (2006) Electron. Lett, 42 (0), pp. 512-514. , Apri

A Precise Sample-and-hold Circuit Topology In Cmos For Low Voltage Applications With Offset Voltage Self Correction

This work describes a new topology for CMOS sample-and-hold circuits in low voltage with self-correction of the offset voltage caused by mismatches in the differential input pair of the operational amplifier. The charge injection of the NMOS switches, although not properly modeled by the simulators, is an important factor and it is minimized in this topology. The results were obtained using the ACCUSiM II simulator on the AMS CMOS 0.8 μm CYE and they reveal the circuit has a reduced error of just 0.03% at the output. © 2002 IEEE.14548Laker, K.R., Sansem, W.M.C., (1994) Design of Analog Integrated Circuits and Systems, , McGraw Hill, incAllen, P.E., Holberg, D.R., (1987) CMOS Analog Circuits Design, , Saunders College PublishingSakurai, S., Ismail, M., (1995) Low Voltage CMOS Operational Amplifiers: Theory, Design and Implementation, , Kluwer Academic PublishersIsmail, M., Fiez, T., (1994) Analog VLSI - Signal and Information Processing, , McGraw HillMcCreary, J.L., Gray, P.R., All-MOS charge redistribution analog-to-digital conversion technique - Part I (1975) IEEE Journal of Solid-State Circuits, SC-10, pp. 371-379. , DecSuarez, R.E., Gray, P.R., Hodges, All-MOS charge redistribution analog-to-digital conversion technique - Part II (1975) IEEE Journal of Solid-State Circuits, SC-10, pp. 379-385. , DecMoreno, R.L., Filho, C.A.R., A MOS analog-switch macromodel for charge injection analysis (1995) First IEEE International Caracas Conference on Devices, Circuits and Systems, , Caracas, Venczucla, De