Study of thermal ageing effects on Rh coating's mechanical performance upon CuCrZr substrate through modeling and experimental methods

Rhodium (Rh) coating on CuCrZr substrate is a promising material option for optical, structural and electrical applications on nuclear fusion reactors. For these applications, Rh coated CuCrZr components subject to long time of thermal ageing due to pre-treatment or normal operation condition. In this paper, both finite element method (FEM) and experimental method were applied to investigate the effects of thermal ageing on mechanical performance of Rh coating after 250 °C, 500 h baking in vacuum. Based on FEM analysis, thermal stresses which concentrate at Rh coating interface is the main source of cracking, and such stresses can be minimized efficiently by introducing a 0.5 μm Au interlayer into the coating layer structure. According to thermal ageing experiments, through-thickness cracking in the Rh coating due to thermal stress releasing and voids generated at the Rh bonding interface caused by Kirkendall effect were the main micro-structure changes in the coating system. The solid-solution hardening caused by significant Cu diffusion into Rh is the dominant factor that affected the Rh coating's hardness. The existing of large amount of cracks in the Rh coating and voids at the Rh coating interface deteriorated the adhesion performance of Rh on CuCrZr substrate by 30%

Multi-physics modeling and Au-Ni/Rh coating assessment for ITER ion cyclotron resonance heating radio-frequency sliding contacts

ITER is a large scale fusion experimental device under construction in Cadarache (France) intended to prove the viability of fusion as an energy source. Ion Cyclotron Resonance Heating (ICRH) system is one of the three heating systems which will supply total heating power of 20 MW (40-55 MHz) up to one hour of operation. Radio-Frequency (RF) contacts are integrated within the antennas for assembly and operation considerations, which will face extremely harsh service conditions, including neutron irradiation, heavy electrical loads (RF current reaches up to 2 kA with a linear current density of 4.8 kA/m) and high thermal loads. Based on the thermal analysis, the contact resistance is expected to be lower than 7 mΩ to keep the maximum temperature on the louvers lower than 250°C. Few weeks of vacuum (~10 -5 Pa) baking at 250°C for outgassing is expected before each plasma experimental campaign, under which the RF contact materials' mechanical properties change and diffusion phenomena between different materials are inevitable. CuCrZr and 316L are proper base materials for ITER RF contact louvers and conductors respectively. In order to improve the RF contact's wear and corrosion resistivity as well as to reduce the contact resistance, Au-Ni and Rh functional layers could be electroplated on CuCrZr and 316L accordingly. The application of the Au-Ni/Rh coating pairs is assessed through the thermal ageing and diffusion tests. Wear and electrical contact performances of the Au-Ni/Rh pairs are deeply studied on a dedicated tribometer operated at ITER relevant conditions

Analyse et amélioration de la robustesse des circuits asynchrones QDI

La conception de circuits intégrés asynchrones, notamment de circuits QDI (Quasi-Delay Insensitive), offrent la possibilité de disposer de circuits très robustes aux conditions environnementales (tension, température) ainsi qu'aux variations des procédés de fabrication. Ces bonnes propriétés sont dues à une conception ne comportant pas d'hypothèses temporelles à l'exception de la fourche isochrone -hypothèse finalement très faible. Ainsi, une variation de la tension se traduit par une réduction de la vitesse de fonctionnement sans pour autant altérer la fonctionnalité du circuit. Cette thèse étudie la robustesse des circuits asynchrones dans des environnements de fonctionnement très sévères susceptibles de mettre en défaut la correction fonctionnelle des circuits asynchrones QDI. Cette situation se présente par exemple quand les transitions des signaux sur les portes deviennent très lentes. Cette situation exceptionnelle peut-être directement provoquée par un environnement agressif (émission électromagnétique, particules à haute énergie, ...) ou par les effets du vieillissement du circuit intégré. Dans un contexte où le circuit est employé à des fins sécuritaires telles que les applications aéronautiques, spatiales ou médicales, il s'avère nécessaire de quantifier les limites de fonctionnement des circuits asynchrones et de trouver des moyens pour améliorer leur robustesse. Ce manuscrit propose une étude complète du comportement des circuits asynchrones et propose des techniques de conception pour en améliorer la robustesse. Les résultats obtenus ont été validés sur des technologies CMOS avancées de ST Microelectronics par des simulations analogiques d'une part, et avec l'aide d'un outil de preuve formelle développé à l'Université British Columbia au Canada d'autre part.The design of self-timed integrated circuits, including QDI (Quasi-Delay Insensitive) circuits, lead to robust circuits against variabilities in manufacturing processes and in running conditions (voltage, temperature). These qualities are consequences of the synthesys flow that does not create timing assumptions excepted a weak one related to isochronic forks. In self-timed circuits, the running speed automatically adjusts to the available supply voltage with no behavioral changes. This work focuses on the self-timed circuit robustness in the context of environments where running conditions can make QDI self-timed circuits failing. For instance, this happens when transition speeds at gate entrances become very slow. This uncommonly encountered situation can be triggered in harsh environments (with electromagnetic disturbences, high-energy particulesdots) or because of age effects on manufactured chips. If the integrated circuit is designed for critical operations such as in aeronautical, spatial or medical applications, the self-timed circuit limits have to be carrefully evaluated and eventually shifted in order to improve the circuit robustness. This publication includes a complete study of the self-timed circuit behaviors and some design proposals in order to enhance the circuit robustness. Experimental results were obtained firstly, during analog simulations targetting advanced CMOS technologies from STMicroelectronics and secondly, using formal methods implemented in a tool from the University of British Columbia.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Formal Verification of C-element Circuits

It is well known that the correct behavior of asynchronous circuits is not guaranteed when the inputs switch too slowly. The erroneous behavior is generally difficult to be spotted by simulation based methods. We applied formal methods to study the analog switching behavior of a full-buffer circuit composed of C-elements. We used our reachability analysis tool COHO to compute all reachable states of two C-element designs and verified several analog properties. Based on these properties, we identified a sufficient condition under which the full-buffer circuit always supports the designed handshaking protocol. We also improved the COHO tool to automate the verification process, reduce error and improve performance. I