The Lipodystrophy Syndrome as a Risk Marker for Cardiovascular Disease in Patients with HIV/AIDS Treated with HAART

Introduction: The classic risk factors for cardiovascular disease in healthy individuals are well known, however, it lacks in the literature the mechanisms that predicts cardiovascular disease in the population living with HIV-AIDS treated with HAART and presenting syndrome lipodystrophy. We aimed to investigate the risk of cardiovascular disease in HIV-AIDS patients treated with HAART and lipodystrophy syndrome. Methods: A search was performed in Medline, SciELO, Lilacs and Cochrane using the intersection between the keywords: "cardiovascular disease", "HIV", "AIDS", "HAART" and "lipodystrophy syndrome". Results: The selected studies demonstrated that metabolic disorders such as hyperlipidemia, central adipose hypertrophy and peripheral lipoatrophy, besides the metabolic syndrome and lipodystrophy are maker clear risks of developing cardiovascular disease in these individuals. Conclusion: The metabolic alterations in HIV-AIDS treated with HAART and presenting lipodystrophy syndrome may potentiate the development of cardiovascular diseases

Charged Particle Tracking in Real-Time Using a Full-Mesh Data Delivery Architecture and Associative Memory Techniques

We present a flexible and scalable approach to address the challenges of charged particle track reconstruction in real-time event filters (Level-1 triggers) in collider physics experiments. The method described here is based on a full-mesh architecture for data distribution and relies on the Associative Memory approach to implement a pattern recognition algorithm that quickly identifies and organizes hits associated to trajectories of particles originating from particle collisions. We describe a successful implementation of a demonstration system composed of several innovative hardware and algorithmic elements. The implementation of a full-size system relies on the assumption that an Associative Memory device with the sufficient pattern density becomes available in the future, either through a dedicated ASIC or a modern FPGA. We demonstrate excellent performance in terms of track reconstruction efficiency, purity, momentum resolution, and processing time measured with data from a simulated LHC-like tracking detector

Em busca de CNNs embarcadas em FPGAs: quantização de rede e infraestrutura HDL para levar CNNs para FPGAs.

Convolutional neural networks (CNNs) have played a prominent role in recent years in the field of computational vision, becoming the dominant approach for recognition and detection tasks. To bring the benefits of CNNs to mobile and embedded devices, quantization strategies have been used to reduce the model size and increase computational efficiency.However, embedding convolutional neural networks is not a matter of only changing the target hardware architecture. Several restrictions of storage, memory, computational resources, and even available energy pose a challenge in bringing the benefits of modern CNN architectures into embedded systems. In the particular case of FPGAs, where energyefficiency meets low-latency and high-bandwidth, this challenges are even more complex given the dominance of general-purpose architectures such as GPUs or CPUs in the field. This work proposes to investigate relevant aspects for a successful implementation of CNNs into embedded systems in general and, in more details, for into FPGAs, where the CNNs benefits may be associated to low-latency and high-bandwith. The state-of-the-art on strategies for efficient computation and storage of CNNs is explored. We show that it is possible to reduce CNN model size by more than 50% while keeping similar classification accuracy without the need for retraining or model adjustment. We also measure the relationship between classification complexity and tolerance to quantization, finding an inverse correlation between the quantization level and dataset complexity. For the specific case of CNNs on FPGAs, details on the required infrastructure for CNN inference are given, presenting a soft-microcontroller and a complete framework capable of supporting CNN implementations.As redes neurais convolucionais (CNNs) têm desempenhado um papel importante nos últimos anos no campo da visão computacional, tornando-se a abordagem dominante para tarefas de reconhecimento e detecção de imagens. Para trazer os benefícios das CNNs para dispositivos móveis e embarcados, estratégias de quantização têm sido usadas para reduzir tamanho de modelo e aumentar a eficiência computacional. No entanto, embarcar CNNs não é uma questão de apenas alterar a arquitetura de hardware de destino. Várias restrições de armazenamento, memória, recursos computacionais e até mesmo energia disponível representam um desafio para trazer os benefícios das arquiteturas de CNN modernas para sistemas embarcados. No caso particular de FPGAs, onde a eficiência energética se alia a baixa latência e alta largura de banda, esses desafios são ainda mais complexos, dado o domínio de arquiteturas de uso geral, como GPUs ou CPUs no campo de estudo. Este trabalho se propõe a investigar aspectos relevantes para a implementação de CNNs em sistemas embarcados em geral e, mais detalhadamente, em FPGAs, onde os benefícios das CNNs podem se associar a baixas latências e alta largura de banda. O estado da arte de estratégias para formas eficientes de processamento e armazenamento de CNNs é explorado. Mostramos que é possível reduzir o tamanho do modelo CNN em mais de 50 %, mantendo a acurácia de classificação sem a necessidade de retreinamento ou ajuste no modelo. Também medimos a relação entre a complexidade de classificação e a tolerância à quantização, encontrando uma correlação inversa entre o nível de quantização e a complexidade do dataset. Para o caso específico de CNNs em FPGAs, são fornecidos detalhes sobre a infraestrutura necessária para inferência de CNN, apresentando um soft-microcontroller e um framework completo capaz de suportar implementações de CNN

A Full Mesh ATCA-based General Purpose Data Processing Board (Pulsar II)

The Pulsar II is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs for LHC experiments. In this technical memo we describe the Pulsar II hardware and its performance, such as the performance test results with full mesh backplanes from di↵erent vendors, how the backplane is used for the development of low-latency time-multiplexed data transfer schemes and how the inter-shelf and intra-shelf synchronization works

Charged Particle Tracking in Real-Time Using a Full-Mesh Data Delivery Architecture and Associative Memory Techniques

We present a flexible and scalable approach to address the challenges of charged particle track reconstruction in real-time event filters (Level-1 triggers) in collider physics experiments. The method described here is based on a full-mesh architecture for data distribution and relies on the Associative Memory approach to implement a pattern recognition algorithm that quickly identifies and organizes hits associated to trajectories of particles originating from particle collisions. We describe a successful implementation of a demonstration system composed of several innovative hardware and algorithmic elements. The implementation of a full-size system relies on the assumption that an Associative Memory device with the sufficient pattern density becomes available in the future, either through a dedicated ASIC or a modern FPGA. We demonstrate excellent performance in terms of track reconstruction efficiency, purity, momentum resolution, and processing time measured with data from a simulated LHC-like tracking detector