Behavioural and educational outcomes following extremely preterm birth : current controversies and future directions

As a consequence of improved survival rates for extremely preterm (EP; <28 weeks of gestation) births, there is a growing body of evidence detailing the impact of extreme prematurity on outcomes throughout childhood and adolescence. Historically, attention first focused on documenting rates of sensory impairments and severe neurodevelopmental disabilities. However, over recent years, there has been growing interest in the impact of EP birth on long term mental health and educational outcomes. In this chapter we review literature relating to the impact of EP birth on attention, social and emotional problems, psychiatric disorders and educational outcomes. We also outline current controversies in the field. In particular, we present emergent research exploring developmental trajectories to determine whether the sequelae associated with EP birth represent a developmental delay or persistent deficit, and we consider what approaches to intervention may be most fruitful in improving behavioural and educational outcomes in this population

InGaAs-InP DHBTs for increased digital IC bandwidth having a 391-GHz f(T) and 505-GHz f max

InP-In0.53Ga0.47As-InP double heterojunction bipolar transistors (DHBT) have been designed for use in high bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 391-GHz f(t), and 505-GHz f(max), which is the highest f(t) reported for an InP DHBT--as well as the highest simultaneous f(t) and f(max) for any mesa HBT. The devices have been aggressively scaled laterally for reduced base-collector capacitance Ccb. In addition, the base sheet resistance rho(s) along with the base and emitter contact resistivities rho(c) have been lowered. The DC current gain beta is approximate to 36 and BV,CEO = 5.1 V. The devices reported here employ a 30-nm highly doped InGaAs base, and a 150-nm collector containing an InGaAs-InAlAs superlattice grade at the base-collector junction. From this device design we also report a 142-GHz static frequency divider (a digital figure of merit for a device technology) fabricated on the same wafer. The divider operation is fully static, operating from f(clk) = 3 to 142.0 GHz while dissipating approximate to 800 mW of power in the circuit core. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies &gt; 100 GHz