2 research outputs found
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Lowering of intralevel capacitance using air gap structures
Interconnect delays, arising in part from intralevel capacitance, are one of the limiting factors in the performance of advanced integrated circuits. In addition, the problem of filling the spaces between neighboring metal lines with an insulator is becoming increasingly severe as aspect ratios increase. We address these problems by intentionally creating a air gap between closely spaced metal lines. The ends of the air gap and reentrant features are then sealed using a spin on dielectric. The entire structure is then capped with silicon dioxide and planarized . Simple modeling of mechanical test structures on silicon predicts an equivalent dielectric constant of 1.9 on features similar to those expected for 0.25 micron technologies. Metal to metal test structures fabricated in a 0.5 micron CMOS technology show that the process can be readily integrated with chemical mechanical polishing and current standard CMOS processes
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An alternative approach to filled--via processing
In order to create sub micron vias between metal layers on silicon IC circuits, the tungsten filled via processes have been in a constant state of development over the past 15 years. Processing is complex, expensive, and difficult to reproduce. The introduction of galvanic cells, via undercutting, and exposed plugs are just some of the plagues that have hit several users of the technology. Discussed in this paper is an alternative approach to the complex tungsten filled via interconnect process. The proposed process yields well at sub micron geometries, is easy to perform, and is inexpensive compared to the tungsten filled via process. Contact resistance improves greatly over the standard tungsten process. The test run achieved a mean value of 0.25 ohms per via compared to historic tungsten process that yields 0.4 ohms per via. The distribution was also excellent with sigma recorded at 0.025 ohms per via