4H-SiC metal oxide semiconductor devices

PhD ThesisMetal oxide semiconductor (MOS) devices are the most important component in advanced integrated circuits (ICs). The success of Si in CMOS technology is owing to the excellent interface formed between Si and SiO2. However, Si-based electronic devices are not suitable to operate in high power, high frequency and high temperature conditions due to material limitations. 4H-SiC with a wide bandgap, high critical electric field, high thermal conductivity and high saturation drift velocity, is an attractive semiconductor material for extreme conditions. However, high quality oxide-semiconductor interfaces are still a major challenge in 4H-SiC MOS devices. This thesis focuses on interface studies of 4H-SiC MOS devices. The main aim is to produce high quality oxide/4H-SiC interfaces by the introduction of an ultrathin SiO2 layer between deposited oxides and 4H-SiC. Ultrathin SiO2 layers can be grown on 4H-SiC using a low thermal budget technique followed by Al2O3 deposition using ALD. N-type and p-type MOS capacitors were fabricated using a gate oxidation of 600 °C for 3 min, which produced SiO2 of thickness 0.7 nm as estimated using ARXPS. Electrical characterisation demonstrates an interface trap density (Dit) of 4-6 × 1011 cm-2eV-1 at 0.2 eV from the conduction and valence band edges. This represents a reduction in Dit by 1-2 orders of magnitude compared to the devices fabricated at 1150 °C for 180 min in the furnace. Furthermore, field effect channel mobility as high as 125 cm2/V.s and a subthreshold slope of 130 mV/dec were obtained from MOSFETs using similar gate stacks. The mobility of MOSFETs decreases with increasing temperature indicating that the electron conductivity is limited by phonon scattering rather than Coulomb scattering, and proves that Dit at the oxide/4H-SiC has been reduced. The ultrathin layer is believed to be a good interface layer between Al2O3 and 4H-SiC. As the temperature and time of the oxidation process increased, resulting in thicker SiO2, the values of Dit increased for both p-type and n-type MOS capacitors. Ultrathin SiO2 layers were also grown underneath a deposited SiO2 layer by N2O annealing at 1175 °C. From n-type MOS capacitor results, the lowest values of Dit obtained were 1.7 × 1012 cm-2eV-1 at 0.2 eV below the conduction band edge, for gate oxides consisting of 60 nm deposited SiO2 followed by 90 min of N2O annealing. This process produced a SiO2 layer 0.68 nm thick, estimated using the Deal-Grove model. The values of Dit increased as the grown SiO2 thicknesses became thicker or thinner than 0.68 nm. This trend is similar to what ii was found in ultrathin SiO2/Al2O3 gate stacks of MOS capacitors proving that 0.7 nm thick is the best thickness of SiO2 to use for 4H-SiC MOS devices. Electrical measurement up to 300 °C proved that these fabricated MOS devices are able to operate well at high temperature. MOSFETs utilizing ultrathin SiO2/Al2O3 gate stacks could retain their enhancement mode behaviour even at high temperature demonstrating the devices capability to be operated in extreme conditions. Both gate stacks also exhibited a low leakage current and were able to withstand electric fields far above 3 MV/cm, which is needed for actual operating system. The scope of these findings points to solutions for the interface challenges in 4H-SiC MOS devices. A thermally grown SiO2 layer 0.7 nm thick exhibited the lowest Dit values for both gate stacks and also produced high field effect channel mobility in MOSFETs. It is anticipated that this fabrication approach will mitigate the oxide/4H-SiC interface problem and contribute towards the development of improved power electronic devices.Ministry of Education Malaysia (MOHE) and in part by the Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka for financially sponsored my study through SLAI scholarship. Special thanks to Engineering and Physical Sciences Research Council (EPSRC), UK for providing the financial support to carry out this research

Compatibility Analysis of Silicon Nitride and Silicon Dioxide on HCI induced LDD MOSFET

Hot-carrier-injection (HCI) is one of important reliability issue under short-channel effect in modern MOSFET devices especially in nano-scaled CMOS technology circuits. The effect of the hot carrier can be reduced by introducing Lightly-Doped-Drain (LDD) structure on the device. The objective of this project is to study the effect of hot carrier in the LDD n-MOSFET. The LDD n-MOSFET is stressed with bias voltage at intervals of stressing time to determine the degradation model in the threshold voltage and drain current. From the parametrical analysis, it shows that the shift in threshold voltage and degradation in the drain current occurred after the MOSFET device is stressed with hot carrier stress test. The rate of threshold voltage shift and degradation of the drain current are dependence to the stressing time applied to the MOSFET device. The hot carrier stress test shows that the device with Si3N4 has smaller voltage shift compared to SiO2 material

IDENTIFICATION OF ARX MODEL FOR THERMOELECTRIC COOLING ON GLASS WINDOWS

Thermoelectric cooling (TEC) is a solid-state heat pump that uses the Peltier effect to dissipate the heat generated by the electronic packaging system. TECs are widely used in aerospace, military, scientific work and industry due to small size, lack of moving parts, and ease of integration. In this study, a cooling system integrated with TEC is developed in a testing area (lecturer’s office) with the aim to reduce the temperature of the hot glass window area due to solar radiation that passes through it. This cooling system used direct TEC, for keeping the cooling temperature on the window to about 26 °C which is equivalent to an air conditioning setting temperature of 26 °C set during the experiment. This work includes experimental and modelling studies conducted on cooling systems integrated with TEC. The main target of this study is to develop a dynamic model of a cooling system integrated with TEC. The black box modelling approach in producing a mathematical model was selected based on the ARX model that corresponds to the actual dynamic state of the cooling system. The best model was finalized based on the best match on curve patterns when comparing the real and estimated models using the system identification tools in MATLAB, and also had the least error. The accuracy of the models was compared and analysed. The results showed that the 4th order of the ARX model produced a higher best fitting and standard deviation values of 78.14% and 0.030769. This system accuracy is almost within the acceptable range for most error calculations in the validation method. In addition, the ARX model is found incapable of achieving the highest fitting due to the losses from the dynamic environment and losses from the TEC itself. Still, the use of this black box model used in this study is a significant variation where system parameters can be identified even offline