Emulation-based Design Errors Identification

Design verification has a large impact on the final testability of a system. The identification and removal of design errors from the initial design steps increases the testing quality of the entire design flow. We propose in this paper to exploit the potentialities of an emulator to accelerate a validation methodology for RTL designs. Alternative emulator configurations are compared in order to evaluate the performance speed-up of the presented methodology. The RTL design functionalities are compared with a System C executable specification model

A 1000X Speed Up for Properties Completeness Evaluation

Verification of circuit description by means of model checking means to write propositions, expressed in some temporal logic, expected to be true on the implementation according to the specification content. Completeness of the set of written properties is still an open problem. We propose a practical approach to the property coverage metrics definition based on fault injection; a combination of model checking, fault simulation and emulation allows to reduce the coverage measure to an affordable task. The application of these three different technologies is illustrated on a real example, on which it leads to the discovery of a missing property in a property set formerly trusted to be complete