Logic-Level Analysis of High-Level Faults

Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available. This paper proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs

A Protected IP-Core Test Generation

A Protected IP-Core Test Generatio

Redundant Functional Faults Reduction by Saboteur Synthesis

High-level descriptions of digital systems are perturbed by using high-level fault models in order to perform functional verification. Fault lists should be accurately created in order to avoid waste of time during ATPG and fault simulation. However, automatic fault injection tools can insert redundant faults which are not symptoms of design errors. Such redundant faults should be removed from the fault list before starting the verification session. This paper proposes an automatic strategy for high-level faults injection, which removes redundant bit coverage faults. An efficient implementation of a bit coverage saboteur is proposed, which allows one to use synthesis for redundant faults removal. Experimental results highlight the effectiveness of the methodology. By using the proposed injection strategy, functional APTG time is reduced and fault coverage is increased

A Fault Tolerant Incremental Design Methodology

Incremental design is the widest applied methodology for VLSI design since, it allows one to produce early versions of the system that, even if not satisfying all requirements, allow one to verify its applicability in the field. The migration from, a system version to a more powerful one is based on the substitution of a module with a more powerful module, which implements new features. This upgrade can introduce errors, which are difficult to be identified during the design since the standard concept of equivalence checking cannot be applied in this context. In fact, the original and the redesigned module can implement different specifications or can achieve the same results under different timing constraints. The paper analyzes this problem and proposes a fault tolerant incremental design methodology able to reduce or avoid such errors

On SAT-applicability to High-Level Testing

On SAT-applicability to High-Level Testin

A Genetic Testing Framework for Digital Integrated Circuits

In order to reduce the time-to-market and simplify gate-level test generation for digital integrated circuits, GA-based functional test generation techniques are proposed for behavioral and register transfer level designs. The functional tests generated can be used for design verification, and they can also be reused at lower levels (i.e. register transfer and logic gate levels) for testability analysis and development. Experimental results demonstrate the effectiveness of the method in reducing the overall test generation time and increasing the gate-level fault coverage

SystemC: A Homogenous Environment to Test Embedded Systems

The SystemC language is becoming a new standard in the EDA field and many designers are starting to use it to model complex systems. SystemC has been mainly adopted to define abstract models of hardware/software components, since they can be easily integrated for rapid prototyping. However, it can also be used to describe modules at a higher level of detail, e.g., RT-level hardware descriptions and assembly software modules. Thus, it would be possible to imagine a SystemC-based design flow, where the system description is translated from one abstraction level to the following one by always using SystemC representations. The adoption of a SystemC-based design flow would be particularly efficient for testing purpose as shown in this paper. In fact, it allows the definition of a homogeneous testing procedure, applicable to all design phases, based on the same error model end on the same test generation strategy. Moreover, test patterns are indifferently applied to hardware and software components, thus making the proposed testing methodology particularly suitable for embedded systems. Test patterns are generated on the SystemC description modeling the system at one abstraction level, theta, they are used to validate the translation of the system to a lower abstraction level. New test patterns are then generated for the lower abstraction level to improve the quality of the test set and this process is iterated for each translation (synthesis) ste

Emulation-based Design Errors Identification

Design verification has a large impact on the final testability of a system. The identification and removal of design errors from the initial design steps increases the testing quality of the entire design flow. We propose in this paper to exploit the potentialities of an emulator to accelerate a validation methodology for RTL designs. Alternative emulator configurations are compared in order to evaluate the performance speed-up of the presented methodology. The RTL design functionalities are compared with a System C executable specification model

Mixing ATPG and Property Checking for Testing HW/SW Interfaces

A critical part of the design of HW/SW systems concerns the definition of the HW/SW interface. Such interfaces do not directly map a functionality of the system description, but they are inferred by the characteristics of the selected programmable device (CPUs, DSPs, ASIPs, etc.). Their addition to the design can modify the behavior of the original system, thus their verification is a hard task. The proposed verification methodology joins functional verification and property checking in order to avoid their respective limitations. The methodology is focused on SystemC descriptions that can be automatically synthesized. This is particularly important since commercial model checking tools work on structural hardware descriptions, which can be obtained by performing rapid prototyping of both HW and SW parts of SystemC models. The proposed approach has been verified on the SystemC model that is the reference synthesis example of one of the most powerful SystemC synthesis environment