Development of a new nuclide generation and depletion code using a topological solver based on graph theory

The problem of calculating the amounts of a coupled nuclide system varying with time especially when exposed to a neutron flux is a well-known problem and has been addressed by a number of computer codes. These codes cover a broad spectrum of applications, are based on comprehensive validation work and are therefore justifiably renowned among their users. However, due to their long development history, they are lacking a modern interface, which impedes a fast and robust internal coupling to other codes applied in the field of nuclear reactor physics. Therefore a project has been initiated to develop a new object-oriented nuclide transmutation code. It comprises an innovative solver based on graph theory, which exploits the topology of nuclide chains and therefore speeds up the calculation scheme. Highest priority has been given to the existence of a generic software interface well as an easy handling by making use of XML files for the user input. In this paper we report on the status of the code development and present first benchmark results, which prove the applicability of the selected approach

JESSI project: advanced technolgoy for 0.25 #mu#m CMOS and below. Subproject: process modules evaluation and integration. Theme 5 Multilevel metallization. Final report

Titanium- and cobaltdisilicide were investigated as material for shallow, low-resistive contacts in a CMOS-metallization system. ITM and DDS were used as self-aligned manufacturing processes. The TiSi_2- and CoSi_2-contact-systems were compared concerning manufacturing process and electrical and physical properties. The CoSi_2-contact-system shows the best properties. CVD-W was used to fill up vias and interconnects. To this a selective tungsten CVD process on CoSi_2 and a blanket deposition process were developed. Due to the excellent selectivity concerning the contact filling, a planarization effect was achieved. Accelerated tests show a high current-carrying capacity for the interconnects. Electromigration was identified as degradation mechanism. PECVD- and TEOS-PECVD-processes were investigated for the deposition of intermetal-dielectrics. An electrical and physical characterization of the layers have been performed. Processes with good step coverage and processes with a planarization effect were specified. Etch-back procedures using photo-resist and spin-on-techniques with various polyimides and a spin-on-glass were investigated in view of a planarization of the chip surface. The best results were achieved using the spin-on-technique with polyimide. (orig.)SIGLEAvailable from TIB Hannover: F94B1507+a+b / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekBundesministerium fuer Forschung und Technologie (BMFT), Bonn (Germany)DEGerman