Modelling road hazards and the effect on AV safety of hazardous failures

Autonomous vehicles (AV) are about to appear on our roads within the next few years. However, to achieve the final breakthrough, not only functional progress is required, but also fundamental safety questions must be solved. Among those, a question demanding special attention is the need to assess the overall safety of an AV and quantify that it is safe enough to take part in normal traffic despite its inherent imperfections. Therefore, this paper describes a probabilistic model, which allows to study how imperfections of an AV perception system and of mechanisms responsible for AV safety (e.g., Safety Monitors), can impact AV safety in the presence of road hazards. We also demonstrate how the model can be used to validate if the AV is safe enough, to understand the criticality of (perception) errors, and to identify areas/parameters that have more influence on safety than others

Impact of Aging on Template Attacks

International audience<p>Template attack is the most powerful side-channel attack from an information theoretic point of view. This attack is launched in two phases. In the first phase (training) the attacker uses a training device to estimate leakage models for targeted intermediate computations, which are then exploited in the second phase (matching) to extract secret information from the target device. Process variation and discrepancy of operating conditions (e.g., temperature) between training and matching phases adversely affect the success probability of the attack. Attack-success degradation is exacerbated when device aging comes into account. Due to aging, electrical specifications of transistors change over time. Thereby, if the training and target devices have experienced different usage time, the attack will be more difficult. Aging alignment between training and target devices is difficult as aging degradation is highly affected by operating conditions and technological variations. This paper investigates the effect of aging on the success rate of template attacks. In particular, we focus on NBTI and HCI aging mechanisms. We mount several attacks on the PRESENT cipher at different temperatures and aging times. Our results show that the attack is more difficult if there is an aging-duration mismatch between the training and target devices.</p

Contemporary Cmos Aging Mitigation Techniques: Survey, Taxonomy, And Methods

The proposed paper addresses the overarching reliability issue of transistor aging in nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of techniques used to model, monitor and mitigate Bias Temperature Instability (BTI) effects in logic circuits are presented. The challenges and overheads of these techniques are covered through the course of this paper. Important metrics of area overhead, power and energy overhead, performance overhead, and lifetime extension are discussed. Furthermore, the techniques are assessed with regards to ease of implementation and the ability to cope with challenges such as increase in manufacturing induced process variations. Finally, a taxonomy of the surveyed techniques is presented to facilitate generalization of the discussed approaches and to foster new inspiring techniques for this important reliability phenomenon leading to advancements in the design of defect-tolerant digital circuits

Spin Orbit Torque memory for non-volatile microprocessor caches

Magnetic spin-based memory technologies are a promising solution to overcome the incoming limits of microelectronics. Nevertheless, the long write latency and high write energy of these memory technologies compared to SRAM make it difficult to use these for fast microprocessor memories, such as L1- Caches. However, the recent advent of the Spin Orbit Torque (SOT) technology changed the story: indeed, it potentially offers a writing speed comparable to SRAM with a much better density as SRAM and an infinite endurance, paving the way to a new paradigm in processor architectures, with introduction of non- volatility in all the levels of the memory hierarchy towards full normally-off and instant-on processors. This paper presents a full design flow, from device to system, allowing to evaluate the potential of SOT for microprocessor cache memories and very encouraging simulation results using this framework