Low inductance 2.5kV packaging technology for SiC switches

The switching speed of power semiconductors has reached levels where conventional semiconductors packages limit the achievable performance due to relatively high parasitic inductance and capacitance. This paper presents a novel packaging structure which employs stacked substrate and flexible printed circuit board (PCB) to obtain very low parasitic inductance and hence feature high switching speed SiC power devices. A half-bridge module aimed at blocking voltage up to 2.5kV has been designed to ac¬commodate 8 SiC JFETs and 4 SiC diodes. Electromagnetic simulation results reveal extremely low in¬ductance values of the major loops. Due to delay delivery of those custom ordered substrate and PCB, the prototyping samples of the designed module have yet been constructed. The up to date results including experimental construction, electrical and thermal performance of the samples will be presented at the conference

SiC MOSFET with a self-aligned channel defined by shallow source-JFET implantation: A simulation study: Poster presented at International Conference on Silicon Carbide & Related Materials, September 29th - October 04th, 2019, Kyoto, Japan

Large cell density within power device is needed to obtain low on state resistance. Cell integration is limited by resolution and overlay accuracy of photolithography. Self-aligned processes, e.g. the self-aligned channel for SiC MOSFET using an over-oxidized polysilicon implantation mask, help to downsale the cell pitch and to increase the cell integration in the device

Schottky diode and method for its manufacturing

The invention disclosure describes a manufacturing method for realizing so-called JBS areas for a unipolar power diode on the basis of diamond. In this special method, an n-doped layer is applied to the typically p-doped drift region, e.g. by means of epitaxial layer growth. The applied n-doped layer is then removed again in defined areas. A photolithographic mask may be applied and the n-doped layer is removed by dry or wet chemical etching. Having structured the JBS areas, the Schottky metal is applied to the entire surface. The resulting JBS structure shields an electric field generated by an applied reverse voltage from the Schottky transition. The reverse voltage from which the Schottky transition is fully shielded can be adjusted by altering the distance between the JBS areas

On a Novel Source Technology for Deep Aluminum Diffusion for Silicon Power Electronics

For the realization of high breakdown voltages in power electronics, a low-cost technology was developed which allows the deep diffusion of aluminum from a physically deposited source. The approach requires only standard process steps already established in the manufacturing of silicon power devices. The sheet concentration of the diffusion profiles realized exceeds with 8E13 cm-2 the ones of comparable implanted and annealed profiles by up to a factor of two. A full numerical analysis of the resulting profiles is provided

Process and design optimization of SiC MOSFET for low on-state resistance: Presentation held at Europe-Korea Conference on Science and Technology, EKC 2019, July 15-18, 2019, Vienna, Austria

Due to outstanding material parameters, silicon carbide (SiC) power devices offer much better electrical and thermal parameters than comparable silicon power devices in the same blocking voltage range. One of the key parameters of the power MOSFET is its on-state resistance, RDS(on) which has to be small, in order to obtain small power loss in a forward current conduction mode. In this work we present how process and design of SiC MOSFET can be optimized for the low on-state resistance. We distinguish different components of the total on-state resistance, which are the substrate and drift resistance; the channel, accumulation and JFET resistance; the source and contact resistance; and we show how each of these components has been minimized for our devices by the recent process developments. In addition to the process optimization, we discuss various ways to improve the SiC MOSFET design, which in general lead to larger cell integration and result in the lower on-state resistance of the device. These are for example a usage of a square elementary cell and an application of the short-channel technology. Results presented in this work are the experimental and simulation data collected during the academic, industrial and joint-research projects at Fraunhofer IISB

Influence of Trench Design on the Electrical Properties of 650V 4H-SiC JBS Diodes

This work presents a design study of customized p+ arrays having influence on the electrical properties of manufactured 4H-SiC Junction Barrier Schottky (JBS) diodes with designated electrical characteristics of 5 A forward and 650 V blocking capabilities. The effect of the Schottky area consuming p+ grid on the forward voltage drop, the leakage current and therefore the breakdown voltage was investigated. A recessed p+ implantation, realized through trench etching before implanting the bottom of the trenches, results in a more effective shielding of the electrical field at the Schottky interface and therefore reduces the leakage current. Customizing the p+ grid array in combination with the trench structure, various JBS diode variants with active areas of 1.69 mm2 were fabricated where as forward voltage drops of 1.58 V @ 5 A with blocking capabilities up to 1 kV were achieved