A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL

Clock generators are an essential and critical building block of any communication link, whether it be wired or wireless, and they are increasingly critical given the push for lower I/O power and higher bandwidth in Systems-on-Chip (SoCs) for the Internet-of-Things (IoT). One recurrent issue with clock generators is multiple-phase generation, especially for low-power applications; several methods of phase generation have been proposed, one of which is phase interpolation. We propose a phase interpolator (PI) that employs the concept of constant-slope operation. Consequently, a low-power highly-linear operation is coupled with the wide dynamic range (i.e., phase wrapping) capabilities of a PI. Furthermore, the PI is powered by a low-dropout regulator (LDO) supporting fast transient operation. Implemented in 65-nm CMOS technology, it consumes 350μ W at a 1.2-V supply and a 0.5-GHz clock; it achieves energy efficiency 4× -15× lower than state-of-the-art (SoA) digital-to-time converters (DTCs) and an integral non-linearity (INL) of 2.5× -3.1× better than SoA PIs, striking a good balance between linearity and energy efficiency

Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation

This article proposes compact expressions for the jitter in clock and data recovery (CDR) circuits based on bang-bang phase detector including the phase noise of the transmitter and receiver oscillators as well as the quantization noise associated with the finite number of phases of the phase interpolator (PI) that align the receiver clock to the incoming data. Different approaches to perform the Early/Late detection on deserialized data and edge samples are compared: the use of majority voting degrades the CDR bandwidth, increasing the impact of the clock jitter on the CDR jitter; on the other hand, counting the single Early/Late occurrences does not degrade the bandwidth but increases the noise related to the finite phases of the PI. The proposed analytical formulas are validated against event-driven behavioral simulations of the CDR system including free-running oscillators as well as phase-locked loop (PLL) for clock generation