Self-timed rings as low-phase noise programmable oscillators

International audienceSelf-timed rings are promising for designing highspeed serial links and system clock generators. Indeed, their architecture is well-suited to digitally control their frequency and to easily adapt their phase noise by design. Self-timed ring oscillation frequency does not only depend on the number of stages as the usual inverter ring oscillators but also on their initial state. This feature is extremely important to make them programmable. Moreover, with such ring oscillators, it is easy to control the phase noise by design. Indeed, 3dB phase noise reduction is obtained at the cost of higher power consumption when the number of stages is doubled while keeping the same oscillation frequency, thanks to the oscillator programmability. In this paper, we completely describe the method to design selftimed rings in order to make them programmable and to generate a phase noise in accordance with the specifications. Test chips have been designed and fabricated in AMS 0.35 μm and in STMicroelectonics CMOS 65 nm technology to verify our models and theoretical claims

Self-Timed Ring Oscillator Based Time-to-Digital Converter: a 0.35μm CMOS Proof-of-Concept Prototype

International audienceThis paper presents an ASIC test chip designed and fabricated in 0.35&mu;m CMOS process to further confirm and evaluate the advantages of the time-to-digital converter (TDC) based on a self-timed ring oscillator (STRO). Three TDCs with different number of STRO stages have been included in this test chip. Most of the measurements are perfectly in accordance with our theoretical claims. The fabricated circuits prove the ability of the proposed TDC architecture to enhance the time resolution by increasing the number of stages. Indeed, three TDCs with L = 9; 23 and 61 have been integrated in the same chip. A 10-bit counter was used to cover a dynamic range of 1.7 &mu;s. The smallest TDC, with L = 9, samples the time intervals with a time resolution of 72.5 ps, while a time resolution of 13.9 ps is obtained with the TDC of L = 61.&lt;br&gt;Index Terms&mdash;Time-to-digital converter, self-timed ring oscillator, time resolution, time measurement, CMOS AMS350 technology, on-the-fly measurement.</p

Nouveau dispositif ultra-précis de mesure du temps basé sur un oscillateur auto-séquencé

National audienc

Nouveau dispositif ultra-précis de mesure du temps basé sur un oscillateur auto-séquencé

National audienc

High Precision Time Measurement using Self-Timed Ring Oscillator based TDC

International audienceA new high resolution time-to-digital converter (TDC) based on a self-timed ring (STR) oscillator is presented. Thanks to the STR unique features, the time resolution of the proposed TDC can be tuned as fine as needed. In addition, on-the-fly time measurements can be carried out on fast non-periodic signals. To provide a proof of concept of this new technique, a design of a 5-stage STR-based TDC has been implemented and simulated using a 28 nm FDSOI CMOS technology

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept

International audienceA new fully digital high resolution time-to-digital converter (TDC) based on a self-timed ring oscillator (STR) is presented. The proposed TDC can virtually achieve as fine as desired time resolution by simply increasing its number of stages thanks to the STR unique features. Moreover, the proposed technique allows on-the-fly time measurement on fast non-periodic signals. The TDC has been implemented using 28 nm FDSOI technology to provide a proof of concept of the proposed method. Simulation results point out the advantage of this TDC in terms of measurement accuracy

Multi-phase low-noise digital ring oscillators with sub-gate-delay resolution

International audienceMulti-phase oscillators are often required to generate multiple clock phases with high frequency, high resolution and low-phase noise. This paper deals with self-timed ring oscillators (STROs), which are a promising solution for designing multi-phase clock generators. In STROs, the phase resolution can be adjusted as fin as desired by simply increasing its number of stages without frequency drop, and this resolution is not limited by the gate delay. In addition, different oscillation frequencies can be obtained by the same STRO depending on its initialization. Thanks to this configurability, $1/N(-10\log(N)dB)$ phase noise reduction is obtained at the cost of higher power consumption when the number of stages is increased $N$ times, while keeping the same oscillation frequency. Moreover, clock jitter in STROs is reduced to the minimum and unavoidable component due to the white noise. Two test-chips have been designed and fabricated in STMicroelectonics CMOS 65 nm and in AMS 350 nm. Most of the measurements are perfectly in accordance with our theoretical claims

Low Phase-Noise CMOS Quadrature Oscillator Based on a (Nx4)-stage Self-Timed Ring

International audienc