Comparison of voice activity detection algorithms for wireless personal communications systems

V oice activity detection (VAD) algorithms have become an in tegral part of many of the recently standardized wireless cellular and P ersonal Communications Systems (PCS). In this paper, we present acomparative study of the performance of three recently proposed VAD algorithms under various acoustical background noise conditions. We also propose new ideas to enhance the performance of a VAD algorithm in wireless PCS speech applications. 1

A hybrid test compression technique for efficient testing of systems-on-a-chip

One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the Geometric-Primitives-Based compression technique with the frequency-directed run-length (FDR) and extended frequency-directed run-length (EFDR) coding techniques. Based on experimental results, we demonstrate the effectiveness of the proposed hybrid compression techniques in increasing the test data compression ratios over those obtained by the Geometric-Primitives-Based compression technique

A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip

One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the Geometric-Primitives-Based compression technique with the frequency-directed run-length (FDR) and extended frequencydirected run-length (EFDR) coding techniques. Based on experimental results, we demonstrate the effectiveness of the proposed hybrid compression techniques in increasing the test data compression ratios over those obtained by the Geometric- Primitives-Based compression technique

An Efficient Test Vector Compression Technique Based on Block Merging

In this paper, we present a new test data compression technique based on block merging. The technique capitalizes on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes advantage of cases where the merged block can be filled by all 0’s or all 1’s. Test data decompression is performed on chip using a simple circuitry that repeats the merged block the required number of times. The decompression circuitry has the advantage of being test data independent. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique compared to previous approaches

An Efficient Test Vector Compression Technique Based on Block Merging

In this paper, we present a new test data compression technique based on block merging. The technique capitalizes on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes advantage of cases where the merged block can be filled by all 0’s or all 1’s. Test data decompression is performed on chip using a simple circuitry that repeats the merged block the required number of times. The decompression circuitry has the advantage of being test data independent. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique compared to previous approaches

Innovation collatérale. Lorsque les sous-produits de l’invention préparent la demande en innovations dans le diagnostic et le traitement du système pelvien

L’innovation prend souvent racine dans l’invention d’une solution originale à un problème donné. Dans le cas du processus d’innovation traité dans cet article, l’histoire commence effectivement ainsi. Des médecins confrontés à un problème de santé, auquel ils peinent à trouver des solutions satisfaisantes, se tournent vers des mécaniciens pour rechercher ensemble une solution innovante, puis en assurer la diffusion. L’article rend compte de la trajectoire de leur coopération. L’article montre que les détours et les innovations inattendues ne sont pas seulement des sous-produits mais qu’elles jouent un rôle dans la dynamique d’innovation dans la mesure où elles contribuent involontairement à préparer la demande pour l’innovation qui était escomptée initialement. L’article contribue ainsi à rendre compte des temporalités complexes de l’innovation et de dynamiques qui sont loin d’être linéaires. Par ailleurs, le fait que les acteurs soient des équipes de chercheurs en collaboration, dont aucun membre n’émerge comme héro de l’histoire, contribue à rendre compte des acteurs souvent laissés dans l’ombre. L’article rend compte de l’épaisseur sociotechnique d’un mode d’existence de l’innovation et la manière dont elles s’insèrent dans un milieu qu’elles ont aussi contribuer à façonner

A class-based clustering static compaction technique for combinational circuits

Static compaction based on test vector merging is a very simple and efficient technique. However, for a highly incompatible test set, merging achieves little reduction. In this paper, we propose a new static compaction technique in which a test vector is decomposed into its atomic components before it is processed. In this way, a test vector that is originally incompatible with all other test vectors in a given test set can be eliminated if its components can be merged with other test vectors

On test vector reordering for combinational circuits

The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such a way that it reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficient test vector reordering technique that significantly reduces both the time and memory complexities of reordering procedures based on fault simulation without dropping. Experimental results demonstrate both the efficiency and effectiveness of our proposed technique

ENHANCING PERFORMANCE OF ITERATIVE HEURISTICS FOR VLSI NETLIST PARTITIONING

ABSTRACT In this paper we, present a new heuristic called PowerFM which is a modification of the well-known Fidducia Mattheyeses algorithm for VLSI netlist partitioning. PowerFM considers the minimization of power consumption due to the nets cut. The advantages of using PowerFM as an initial solution generator for other iterative algorithms, in panicular Genetic Algorithm (GA) and Tabu Search (TS), for multiobjective optimization is investigated. A series of experiments are conducted on ISCAS-85/89 benchmark circuits to evaluate the efficiency of the PawerFM algorithm. Results suggest that this heuristic would provide a good starting solution for multiobjective optimization using iterative algorithms