Effects of treatment with GH alone or in combination with LHRH analog on bone mineral density in pubertal GH-deficient patients

The aim of the present study was to assess the impact of treatment with GH with or without LHRH analog (LHRH-A) on bone mineralization of GH-deficient adolescents. We studied 17 pubertal, treatment-naive, GH-deficient patients (10 girls and 7 boys) in a prospective, randomized trial. Mean chronological age and mean bone age were 14.1 ± 0.4 and 11.3 ± 0.3 yr, respectively, at the beginning of the study. Treatment with GH + LHRH-A (n = 7) or GH alone (n = 10) started simultaneously. Nutropin was administered at a dose of 0.1 U/kg per day sc until patients reached near final height (NFH), defined as a bone age of 14 yr in girls and 16 yr in boys. Mean time of GH therapy in the patients treated with GH + LHRH-A was 4.8 ± 0.5 yr and in the patients treated with GH alone 2.9 ± 0.7 yr. Lupron was administered at a dose of 300 μg/kg every 28 d im for 3 yr. Bone mineral density (BMD) was assessed yearly by dual-energy x-ray absorptiometry at the lumbar spine (L2-L4) and femoral neck at the beg

Reducing control overhead in dataflow architectures

In recent years, computer architects have proposed tiled architectures in response to several emerging problems in processor design, such as design complexity, wire delay, and fabrication reliability. One of these architectures, WaveScalar, uses a dynamic, tagged-token dataflow execution model to simplify the design of the processor tiles and their interconnection network and to achieve good parallel performance. However, using a dataflow execution model reawakens old problems, including the instruction overhead required for control flow. Previous work compiling the functional language Id to the Monsoon Dataflow System found this overhead to be 2−3 × that of programs written in C and targeted to a MIPS R3000. In this paper, we present and analyze three compiler optimizations that significantly reduce control overhead with minimal additional hardware. We begin by describing how to translate imperative code into dataflow assembly and analyze the resulting control overhead. We report a similar 2 − 4 × instruction overhead, which suggests that the execution model, rather than a specific source language or target architecture, is responsible. Then, we present the compiler optimizations, each of which is designed to eliminate a particular type of control overhead, and analyze the extent to which they were able to do so. Finally, we evaluate the effect using all optimizations together has on program performance. Together, the optimizations reduce control overhead by 80 % on average, increasing application performance between 21-37%

The WaveScalar architecture

Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, however, is an open challenge that conventional superscalar designs will not be able to meet. We present WaveScalar as a scalable alternative to conventional designs. WaveScalar is a dataflow instruction set and execution model designed for scalable, low-complexity/high-performance processors. Unlike previous dataflow machines, WaveScalar can efficiently provide the sequential memory semantics that imperative languages require. To allow programmers to easily express parallelism, WaveScalar supports pthread-style, coarse-grain multithreading and dataflow-style, fine-grain threading. In addition, it permits blending the two styles within an application, or even a single function. To execute WaveScalar programs, we have designed a scalable, tile-based processor architecture called the WaveCache. As a program executes, the WaveCache maps the program’s instructions onto its array of processing elements (PEs). The instructions remain at their processing elements for many invocations, and as the working set of instructions changes, the WaveCache removes unused instructions and maps new ones in their place. The instructions communicate directly with one another over a scalable, hierarchical on-chip interconnect, obviating the need for long wires an