An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration

In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transactionbased protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL. Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143mm in a 0.13m technology, and runs at 500 MHz

Hot or not? Discovery and characterization of a thermostable alditol oxidase from Acidothermus cellulolyticus 11B

We describe the discovery, isolation and characterization of a highly thermostable alditol oxidase from Acidothermus cellulolyticus 11B. This protein was identified by searching the genomes of known thermophiles for enzymes homologous to Streptomyces coelicolor A3(2) alditol oxidase (AldO). A gene (sharing 48% protein sequence identity to AldO) was identified, cloned and expressed in Escherichia coli. Following 6xHis tag purification, characterization revealed the protein to be a covalent flavoprotein of 47 kDa with a remarkably similar reactivity and substrate specificity to that of AldO. A steady-state kinetic analysis with a number of different polyol substrates revealed lower catalytic rates but slightly altered substrate specificity when compared to AldO. Thermostability measurements revealed that the novel AldO is a highly thermostable enzyme with an unfolding temperature of 84 °C and an activity half-life at 75 °C of 112 min, prompting the name HotAldO. Inspired by earlier studies, we attempted a straightforward, exploratory approach to improve the thermostability of AldO by replacing residues with high B-factors with corresponding residues from HotAldO. None of these mutations resulted in a more thermostable oxidase; a fact that was corroborated by in silico analysis

Compaan: Deriving Process Networks from Matlab for Embedded Signal Processing Architectures.

This paper presents the Compaan tool that automatically transforms a nested loop program written in Matlab into a processnetwork specification. The process network model of computation fits better with the new emerging kind of embedded architectures that use coprocessors. Processnetworkscan describe both fine-grained andcoarsegrained parallelism, making the mapping of the applications easier. Keywords Process Networks, Matlab, Mapping, Embedded Architectures. 1

A parallel processor for fast execution of time-adaptive Jacobi algorithms

In this paper we take the class of Jacobi-type algorithms and present a systematic way to derive an architecture for execution of the time adaptive QR and QR \Gamma1 algorithms, two members of the class. We know that Jacobi-type algorithms find natural expression in Cordic arithmetic and that high-throughput implementations ask for parallel operating pipelined Cordic processor elements. Based on this knowledge, we perform algorithmic transformations, exploiting class specific properties, to reduce critical paths, increase throughput and improve structure utilization. The techniques illustrated in the paper are currently used to derive the specifications of a `class optimal' processor into which several Jacobi-type algorithms execute simultaneously. Keywords--- parallel processors, Jacobi-type algorithms, algorithmic transformations, pipelined processors, Cordic-arithmetic. I. Introduction Matrix computations are increasingly finding application in real-time signal processing. A num..

PROCEEDINGS OF PROGRESS 2001, 2ND WORKSHOP ON EMBEDDED SYSTEMS 1 A Router Architecture for Networks on Silicon

Abstract — To deal with the increasing design complexity of integrated systems reuse of intellectual property (IP) blocks is promoted. A system architecture then becomes a composition of a heterogeneous set of such IP blocks together with a network that interconnects these blocks. The main challenge of system design therefore shifts from computation (IP blocks) to communication and storage (interconnect and memories). This means that applications become dynamic compositions of IP blocks which requires that the network is scalable (in the number of attached IP blocks), programmable and behaves predictably under the traffic offered by those blocks. As the feature size decreases the relative cost of wires increases. We therefore search for an interconnect network that efficiently uses wires through sharing by introducing routers. For a flexible and efficient solution at least two traffic classes must be support by the network, viz., guaranteedthroughput (GT) and best-effort (BE). For GT traffic communication channels are set up to transport data between IP blocks (possibly via memory). Best-effort traffic is never lost, but no latency or through-put guarantees are given. We also address the conflicting requirements of GT and BE traffic [1]. Our router is packet-switched and uses input-queuing with an efficient packet/flit scheduling [2] for BE traffic, whereas efficient time division multiplexing scheme is used is used for GT traffic. The focus of this paper is on the derivation of a costeffective router and network suitable for on-chip integration. I

Deadlock Prevention in sc Æthereal Protocol

Contains fulltext : 32388.pdf (preprint version ) (Open Access

An Approach for the Mapping of Jacobi Algorithms onto a Jacobi Specific Dataflow Processor

Dedicated application specific processors often suffer from long design times and short lifecycles. It makes sense to confine ourselves to the class of Jacobi algorithms, because this enables us to come up with an initial template for a processing element (PE). The processor consists of a series of such PEs. The PE itself is composed of four units. One of these units is the memory and contains a series of logical storage structures (LSSs). These LSSs can be seen as data re-ordering units. At the write port an LSS behaves like a queue. An LSS is special in that a single command can be used to request a whole sequence of data elements. The problem is to map the algorithms onto a series of PEs. Our point of departure is the single assignment code (SAC) of the algorithms to be mapped. Given an algorithm, we go through a number of transformations, such that we eventually arrive at a specification whose semantics corresponds with that of the processor. To verify the correctness of the transf..