High-Level Synthesis for Scan

This Technical Note contains a preprint of a paper submitted to the 15th IEEE VLSI Test Symposium to be held on April 27-30, 1997 at Monterey, CA

ATPG for Scan Chain Latches and Flip-Flops

This Technical Note contains a preprint of a paper submitted to the 15th IEEE VLSI Test Symposium to be held on April 27-30, 1997 at Monterey, CA. Funding: This work was supported in part by the Ballistic Missile Defense Organization, Innovative Science and Technology (BMDO/IST) Directorate and administered through the Department of the Navy, Office of Naval Research under Grant No. N00014-92-J-1782, in part by the Advanced Research Projects Agency under Contract No. DABT63-94-C-0045, and in part by the National Science Foundation under Grant No. MIP-9107760. It was also funded in part by Cirrus Logic. Copyright 1996 by the Center for Reliable Computing, Stanford University. All rights reserved, including the right to reproduce this report, or portions thereof, in any form. Center for Reliable Computing Computer System Lab Departments of Electrical Engineering and Computer Science Stanford University Stanford, CA 94305 Tel: (415) 723-1258 Fax: (415) 725-7398 e-mail: [email protected], [email protected] Suggested Topics: ATPG, Scan Chain, Functional Faults