Partition and propagate: an error derivation algorithm for the design of approximate circuits

Inexact hardware design techniques have become popular in error-tolerant systems, where energy efficiency is a primary concern. Several techniques aim to identify circuit portions that can be discarded under an error constraint, but research on systematic methods to determine such error is still at an early stage. We herein illustrate a generic, scalable algorithm that determines the influence of each circuit gate on the final output. The algorithm first partitions the graph representing the circuit, then determines the error propagation model of the resulting subgraphs. When applied to existing approximate design frameworks, our solution improves their efficiency and result quality

Models of computation for embedded system design

In the near future, most objects of common use will contain electronics to augment their functionality, performance, and safety. Hence, time-tomarket, safety, low-cost, and reliability will have to be addressed by any system design methodology. A fundamental aspect of system design is the specification process. We advocate using an unambiguous formalism to represent design specifications and design choices. This facilitates tremendously efficiency of specification, formal verification, and correct design refinement, optimization, and implementation. This formalism is often called model of computation. There are several models of computation that have been used, but there is a lack of consensus among researchers and practitioners on the "right" models to use. To the best of our knowledge, there has also been little effort in trying to compare rigorously these models of computation. In this paper, we review current models of computation and compare them within a framework that has been r..

Embedded system design specification: merging reactive control and data computation

We have presented two language extensions for C and Java for embedded system specification, simulation and implementation. The two languages JESTER and ECL build upon the ESTEREL synchronous semantic foundation that provides support for waiting, concurrency and preemption. They nicely support specification of mixed control/data modules. The compilation is performed by splitting the source code into reactive ESTEREL code (as large as possible, in the current implementation) and data-dominated C or Java code. The large reactive portion can be robustly optimized and synthesized to either hardware or software, while the C residual code must be either implemented in software as is or the user must provide a a hardware implementation