Atomic step motion during the dewetting of ultra-thin films

We report on three key processes involving atomic step motion during the dewetting of thin solid films: (i) the growth of an isolated island nucleated far from a hole, (ii) the spreading of a monolayer rim, and (iii) the zipping of a monolayer island along a straight dewetting front. Kinetic Monte Carlo results are in good agreement with simple analytical models assuming diffusion-limited dynamics.Comment: 7 pages, 5 figure

Characterization and physical modeling of endurance in embedded non-volatile memory technology

Transient and endurance mechanisms in highperformance embedded non-volatile memory flash devices are investigated in detail. An extraction methodology combining measurements on equivalent transistors and flash cells is proposed to discriminate the effects of defects on program/erase (P/E) efficiencies and on DC characteristics. A semi-analytical multiphonon-assisted charge trapping model is used to investigate the role and the impact of trapped charges on channel hotelectron injection and Fowler-Nordheim efficiencies, threshold voltage variations and endurance characteristics. © 2011 IEEE

Growth and characterization of gold catalyzed SiGe nanowires and alternative metal-catalyzed Si nanowires

The growth of semiconductor (SC) nanowires (NW) by CVD using Au-catalyzed VLS process has been widely studied over the past few years. Among others SC, it is possible to grow pure Si or SiGe NW thanks to these techniques. Nevertheless, Au could deteriorate the electric properties of SC and the use of other metal catalysts will be mandatory if NW are to be designed for innovating electronic. First, this article's focus will be on SiGe NW's growth using Au catalyst. The authors managed to grow SiGe NW between 350 and 400°C. Ge concentration (x) in Si1-xGex NW has been successfully varied by modifying the gas flow ratio: R = GeH4/(SiH4 + GeH4). Characterization (by Raman spectroscopy and XRD) revealed concentrations varying from 0.2 to 0.46 on NW grown at 375°C, with R varying from 0.05 to 0.15. Second, the results of Si NW growths by CVD using alternatives catalysts such as platinum-, palladium- and nickel-silicides are presented. This study, carried out on a LPCVD furnace, aimed at defining Si NW growth conditions when using such catalysts. Since the growth temperatures investigated are lower than the eutectic temperatures of these Si-metal alloys, VSS growth is expected and observed. Different temperatures and HCl flow rates have been tested with the aim of minimizing 2D growth which induces an important tapering of the NW. Finally, mechanical characterization of single NW has been carried out using an AFM method developed at the LTM. It consists in measuring the deflection of an AFM tip while performing approach-retract curves at various positions along the length of a cantilevered NW. This approach allows the measurement of as-grown single NW's Young modulus and spring constant, and alleviates uncertainties inherent in single point measurement

Modeling study of capacitance and gate current in strained High–K Metal gate technology: impact of Si/SiO2/HK interfacial layer and band structure model

The importance of developing predictive modeling tools has considerably increased with the diffusion of nanoscale technologies, in which strained layers and heterojunctions determine the materials modeling complexity. A self--consistent Poisson--Schroedinger solver based on a full-band k.p method within the envelope-function approximation has been developed and validated on large test structures, studying the oxide capacitance for various gate stacks. Among the effects governing the electrostatics of the devices we have studied (i) the impact of band structure models of the oxide, (ii) of the semiconductor, and (iii) the impact of the Si/SiO2 interfacial layers. The predictions of 2 advanced full band (FB) models (tight binding model and 30-bands k.p model) are compared to simpler 6-band k.p and 3-band effective mass approximation. In FB models, the oxides have been treated as pseudo zinc-blende materials, adjusting the model parameters using ab-initio simulations to match the band structure obtained from first principles. The importance of having such accurately calibrated models relies in the reduced computational time of EMA models with respect to FB models. Additionally we performed 2D TCAD simulations with a commercial simulation package to assess the predictions of the models implemented in TCAD tools. Finally we assessed the importance of accurate electrostatic modeling on gate tunneling current

Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model

This paper investigates and models Gate Induced Drain Leakage (GIDL) for a wide variety of high voltage devices with different low doped drain (LDD) structures. Based on TCAD simulations, we propose semi-analytical a pseudo-2D model for Gate induced Drain leakage. This model includes a complete modeling of the overlap region accounting for technological process and bulk bias dependency through detailed electric field description

Characterization and 3D TCAD simulation of NOR-type flash non-volatile memories with emphasis on corner effects

International audienceThe impact of 3D device architecture in aggressively scaled embedded non-volatile memories has been investigated by means of experiments and 3D TCAD simulations. A complete 3D calibration methodology covering DC and transient operating regimes has been introduced and validated against measurements for different technological options. This approach has been employed to determine the key features for device optimization. In particular, shallow trench isolation corners around the active area have been identified as critical regions of the memory cell for program and erase operations, as well as for gate coupling ratio optimization

Characterization and modelling of gate current injection in embedded non-volatile flash memory

Hot Carrier Injection (HCI) is investigated from the experimental and modelling perspectives. Extensive characterization of HCI is performed on ash devices to overcome the difculties arising from direct gate injection measurements. Furthermore, a semi-analytical approach has been developped, capable of modelling both ash cell\u2019s electrostatics during transient operation and gate current under HCI by a non-local model valid for long and short channel devices

On the accuracy of current TCAD hot carrier injection models in nanoscale devices

In this work, the hot electron injection models presently available for technology support have been investigated within the context of the development of advanced embedded non-volatile memories. The distribution functions obtained by these models (namely the Fiegna Model \u2013 FM [1], the Lucky Electron Model \u2013 LEM [2] and the recently implemented Spherical Harmonics Expansion of the Boltzman\u2019s Transport Equation \u2013 SHE [3]), have been systematically compared to rigorous Monte Carlo (MC) results [4], both in homogeneous and device conditions. Gate-to-drain current ratio and gate current density simulation has also been benchmarked in device simulations. Results indicate that local models such as FM, can partially capture the channel hot electron injection, at the price of model parameter adjustments. Moreover, at least in the device and field condition considered in this work, an overall better agreement with MC simulations has been obtained using the 1st order SHE, even without any particular fitting procedure. Extending the results presented in [3] by exploring shorter gate lengths and addressing the floating gate voltage dependence of the gate current, this work shows that the SHE method could contribute to bridge the gap between the rigorous but time consuming MC method and less rigorous but suitable TCAD local models

Embedded non-volatile memory study with surface potential based model

International audienc