A multidimensional measure of polypharmacy for older adults using the Health and Retirement Study

Polypharmacy is commonly defined based on the number of medications taken concurrently using standard cut-offs, but several studies have highlighted the need for a multidimensional assessment. We developed a multidimensional measure of polypharmacy and compared with standard cut-offs. Data were extracted for 2141 respondents of the 2007 Prescription Drug Survey, a sub-study of the Health Retirement Study. Latent classes were identified based on multiple indicators of polypharmacy, including quantity, temporality and risk profile. A four-class model was selected based on fit statistics and clinical interpretability: ‘High risk, long-term’ (Class 1), ‘Low risk, long-term’ (Class 2), ‘High risk, short-term’ (Class 3), and ‘High risk for drug interactions, medium-term, regular’ (Class 4). Classes differed regarding sex, cohabitation, disability and multimorbidity. Participants in the ‘low risk’ class tended to be male, cohabitating, and reported fewer health conditions, compared to ‘high risk’ classes. Polypharmacy classes were compared to standard cut-offs (5+ or 9+ medications) in terms of overlap and mortality risk. The three ‘high risk’ classes overlapped with the groups concurrently taking 5+ and 9+ medications per month. However, the multidimensional measure further differentiated individuals in terms of risk profile and temporality of medication taking, thus offering a richer assessment of polypharmacy

Development of a front end ASIC for Dark Matter directional detection with MIMAC

A front end ASIC (BiCMOS-SiGe 0.35 \mum) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (a few keV) tracks with a gaseous \muTPC. The development of this front end ASIC is a key point of the project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronics. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2 x 96 strips of pixels are monitored.Comment: 12 pages, 10 figure

Knowledge graph prediction of unknown adverse drug reactions and validation in electronic health records

Unknown adverse reactions to drugs available on the market present a significant health risk and limit accurate judgement of the cost/benefit trade-off for medications. Machine learning has the potential to predict unknown adverse reactions from current knowledge. We constructed a knowledge graph containing four types of node: drugs, protein targets, indications and adverse reactions. Using this graph, we developed a machine learning algorithm based on a simple enrichment test and first demonstrated this method performs extremely well at classifying known causes of adverse reactions (AUC 0.92). A cross validation scheme in which 10% of drug-adverse reaction edges were systematically deleted per fold showed that the method correctly predicts 68% of the deleted edges on average. Next, a subset of adverse reactions that could be reliably detected in anonymised electronic health records from South London and Maudsley NHS Foundation Trust were used to validate predictions from the model that are not currently known in public databases. High-confidence predictions were validated in electronic records significantly more frequently than random models, and outperformed standard methods (logistic regression, decision trees and support vector machines). This approach has the potential to improve patient safety by predicting adverse reactions that were not observed during randomised trials

Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics

The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

International audienceA 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide

A low power and low signal 5-bit 25MS/s pipelined ADC for monolithic active pixel sensors

For CMOS monolithic active pixels sensor readout, we developed a 5 bit low power analog to digital converter using a pipelined architecture. A non-resetting sample and hold stage is included to amplify the signal by a factor of 4. Due to the very low level of the incoming signal, this first stage compensates both the amplifier offset effect and the input common mode voltage dispersion. The converter consists of three 1.5 bit sub-ADC and a 2 bit flash. We present the results of a prototype, made of eight ADC channels. The maximum sampling rate is 25MS/s. The total DC power consumption is 1.7mW/channel on a 3.3V supply voltage recommended for the process. But at a reduced 2.5V supply, it consumes only 1.3mW. The size of each ADC channel layout is only 43μm*1.43mm. This corresponds to the pitch of two pixel columns each one would be 20μm wide. The full analog part of the converter can be quickly switched to a standby idle mode in less than 1μs; thus reducing the power dissipation to a ratio better than 1/1000. This fast shutdown is very important for the ILC vertex detector as the total DC power dissipation becomes directly proportional to the low beam duty cycle

Experimental study of a liquid Xenon PET prototype module

A detector using liquid Xenon in the scintillation mode is studied for Positron Emission Tomography (PET). The specific design aims at taking full advantage of the liquid Xenon properties. It does feature a promising insensitive to any parallax effect. This work reports on the performances of the first LXe prototype module, equipped with a position sensitive PMT operating in the VUV range (178 nm).Comment: Proc. of the 7th International Workshops on Radiation Imaging Detectors (IWORID-7), Grenoble, France 4-7 July 200

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

soumis à JINSTA 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35µm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1µs. The size for the layout is 80µm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20µm wide

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for monolithie active pixel sensors

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide