378 research outputs found
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GENUS : a generic component library for high level synthesis
This report describes the organization of GENUS, a generic component library for high level synthesis. Generic components and instances in GENUS are organized into hierarchical classes, with the component type stored at the root of the hierarchy, and particular instances stored at the leaves. This permits a consistent representation of generic components which may be used by a variety of synthesis and analysis tools. The appendix contains the description of the GENUS generator library
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Detailed modeling of processors and high performance cycle-accurate
simulators are essential for today's hardware and software design. These
problems are challenging enough by themselves and have seen many previous
research efforts. Addressing both simultaneously is even more challenging, with
many existing approaches focusing on one over another. In this paper, we
propose the Reduced Colored Petri Net (RCPN) model that has two advantages:
first, it offers a very simple and intuitive way of modeling pipelined
processors; second, it can generate high performance cycle-accurate simulators.
RCPN benefits from all the useful features of Colored Petri Nets without
suffering from their exponential growth in complexity. RCPN processor models
are very intuitive since they are a mirror image of the processor pipeline
block diagram. Furthermore, in our experiments on the generated cycle-accurate
simulators for XScale and StrongArm processor models, we achieved an order of
magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator.Comment: Submitted on behalf of EDAA (http://www.edaa.com/
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Behavioral modeling of DRACO : a peripheral interface ASIC
This paper describes the behavioral modeling of DRACO, a peripheral interface Application Specific Integrated Circuit (ASIC) developed by Rockwell International for numerical control applications. The behavioral model was generated from a data sheet of the fabricated chip, which primarily described the chip's input-output functionality, physical and operational characteristics, and a functional block diagram. The data sheet contained very little abstract behavioral information. This report describes the abstract behavioral model of the DRACO chip, and uses flowcharts and VHDL to capture the behavior. The behavioral model was developed through reverse engineering of the data sheet description, supplemented by further consultation with designers of the DRACO ASIC at Rockwell Intemational. The report describes typical behavioral test sequences that were applied to the DRACO VHDL model to verify its correctness. The appendices contain the original DRACO datasheet and the VHDL code used to capture DRACO's behavior
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Bridging high-level synthesis to RTL technology libraries
The output of high-level synthesis typically consists of a netlist of generic RTL components and a state sequencing table. While module generators and logic synthesis tools can be used to map RTL components into standard cells or layout geometries, they cannot provide technology mapping into the data book libraries of functional RTL cells used commonly throughout the industrial design community. In this paper, we introduce an approach to implementing generic RTL components with technology-specific RTL library cells. This approach addresses the criticism of designers who feel that high-level synthesis tools should be used in conjunction with existing RTL data books. We describe how GENUS, a library of generic RTL components, is organized for use in high-level synthesis and how DTAS, a functional synthesis system, is used to map GENUS components into RTL library cells
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Benchmarking for high-level synthesis
This paper discusses issues in benchmarking for synthesis, and suggests techniques for the comparison of benchmark descriptions, the synthesis tools used, as well as the synthesized designs finally generated. We propose a classification scheme for the assumptions made for the comparison of different synthesis tools, and present an Assumptions Chart that can be used to visualize different benchmarks, tools and synthesis results. We illustrate application of this Assumptions Chart using synthesis experiments that were conducted on some sample High-Level Synthesis Workshop bench-marks
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EXEL : a language for interactive behavioral synthesis
This paper describes a new input language for behavioral synthesis called EXEL. EXEL is a powerful language that permits the user to specify partially designed structures in the language. It employs a mixed graphic/textual user interface to enhance user interactivity. EXEL's design model is comprehensive: it permits specification of synchronous and asynchronous behavior, and allows specification of general timing constraints. A flexible type construct permits the user to define operators and components to be used in the description. Finally, it simplifies compilation by using a small set of constructs for specifying timing and asynchronouos behavior. The compiler for EXEL runs on SUN-3 workstations and is written in C and SUNVIEW
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Design considerations for limited connectivity VLIW architectures
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Translating BIF into VHDL : algorithms and examples
This report describes an algorithm for automatically translating BIF system-level behavioral descriptions to behavioral VHDL. BIF is a new intermediate representation for behavioral synthesis, based on annotated state tables that supports user control of the synthesis process by allowing specification of partial design structures, unit bindings, and modification of the design at various levels of abstraction. This flexibility creates a need for behavioral verification of the design at each level of abstraction to provide feedback information to the user. Since VHDL is a well formalized, simulatable language it makes an ideal target for translation.We discuss the complexities inherent in representing BIF's hierarchical state specifications in VHDL and examine a general model for the combined representation of hierarchy, timing, concurrency, and arbitrary state transitions in VHDL.We conclude the report with several examples from a recently implemented translator
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BIF : a behavioral intermediate format for high level synthesis
This report describes a new intermediate format for behavioral synthesis systems, based on annotated state tables. It supports user control of the synthesis process by allowing specification of partial design structures, user-bindings and user modification of compiled designs. It is a simple and uniform representation that can be used as an intermediate exchange format for various behavioral synthesis tools. The format captures synchronous and asynchronous behavior, and serves as a good interface to the user by linking behavior and structure at each level of abstraction in the behavioral synthesis process
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